TimTamSlam
Newbie level 2
I am using GHDL and GTKWAVE to help with simulation
Thanks for looking at my post. I am learning vhdl and attempting to look into using records. I have been reading the article https://www.gaisler.com/doc/vhdl2proc.pdf, which preaches the ease of use and importance of using records to pass data, keep code reusable, and make it easily readable (sounds nice right). Well so I can understand vhdl I have been practicing by first trying to make a simple vhdl entity then an associated testbench. I could not figure out how to write the associated test bench for the vhdl in the article but looked for some simple examples on the web and came across this article at nand land https://www.nandland.com/vhdl/examples/example-record.html. I then tried writing a testbench for this entity like so:
which does not complain when analyzed or run, the only problem is that when I go into GTKwave I only see my clock signal or the signal
. I was thinking that I would see my records also in GTKwave, is this wishful thinking or am I missing something.
Thanks for looking at my post. I am learning vhdl and attempting to look into using records. I have been reading the article https://www.gaisler.com/doc/vhdl2proc.pdf, which preaches the ease of use and importance of using records to pass data, keep code reusable, and make it easily readable (sounds nice right). Well so I can understand vhdl I have been practicing by first trying to make a simple vhdl entity then an associated testbench. I could not figure out how to write the associated test bench for the vhdl in the article but looked for some simple examples on the web and came across this article at nand land https://www.nandland.com/vhdl/examples/example-record.html. I then tried writing a testbench for this entity like so:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.example_record_pkg.all;
entity Records_Ex_tb is
end Records_Ex_tb;
architecture behavior of Records_Ex_tb is
component example_record
port(
i_clk : in std_logic;
i_fifo : in t_FROM_FIFO;
o_fifo : out t_TO_FIFO := c_TO_FIFO_INIT
);
end component;
-- signals
signal i_clk : std_logic;
signal i_fifo : t_FROM_FIFO;
signal o_fifo : t_TO_FIFO;
begin
uut : example_record port map (i_clk => i_clk, i_fifo => i_fifo, o_fifo => o_fifo);
clk_proc : process
begin
i_clk <= '0';
wait for 1 ns;
i_clk <= '1';
wait for 1 ns;
end process;
stim_proc : process
begin
wait for 10 ns;
assert false report "end of test";
wait;
i_fifo.wr_full <= '1';
end process;
end behavior;
which does not complain when analyzed or run, the only problem is that when I go into GTKwave I only see my clock signal or the signal
Code:
r_WR_DATA