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library ieee;
use ieee.std_logic_1164. all ;
use ieee.numeric_std. all ;
entity bcd_adder is
port (
a,b : in unsigned(3 downto 0);
carry_in : in std_logic;
sum : out unsigned(3 downto 0);
carry : out std_logic);
end bcd_adder;
architecture arch of bcd_adder is
begin
process(a,b)
variable sum_temp : unsigned(4 downto 0);
begin
sum_temp := ('0' & a) + ('0' & b) + ("0000" & carry_in);
if (sum_temp > 9) then
carry <= '1';
sum <= resize((sum_temp + "00110"),4);
else
carry <= '0';
sum <= sum_temp(3 downto 0);
end if ;
end process;
end architecture;
why not instantiate it 4 times?>
I don't know VHDL and I'm not even willing to learn it. So the term instantiate is meaningless to me.what?
I want you to tell me exactly how to do an instantiation with example code of doing it 4 times and...z522msn said:can you explain?
...better yet! can you do it for me so I don't have to lift a finger or put any effort into learning anything...even how to use Google and the terms "VHDL instantiation" https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=vhdl%20instantiationz522msn said:can you help me to design it??
Can you write the testbench for me and run the simulations for me and verify it's working, then send the code to my professor and ask them to give me a good grade in the class.
thanks!!!!!!!!