AXI FIFO does not work

[u24c02]

Dear all,

Now I'm trying to implement with axi4lite FIFO in the vivado.

I add 3 IPs, one master, one interconnection, axi4lite FIFO.
The problem is that Fifo does not write and read when I tried write and read.

Here is waveform.


Would you please let me know what should I do to solve this problem or any hint?

 

[vGoodtimes]

my guess would be that aresetn is configurable or different for the interface, with one being registered and inverted. notice one interface is ready until 1 cycle after aresetn goes high. The signals in the middle appear ok, with ready+valid being followed by another signal being marked valid.