assignment statement in .vnetlist

[p.sivakumar]

Hi

what is the Assignment statement in .v netlist ?

Thanks
Sivakumar

 

[spauls]

netlist that contains "assign" statement .
A good and clean netlist should not contain these statements.

 

[p.sivakumar]

Hi

if it contains assign statement what will happen in the design ?and what it represents actually ? can you explain?

Thanks
Sivakumar

 

[avimit]

Assign Statement in Verilog simply connects two wire types, with or without any combinational logic in between. It is legal to have it in netlist, but usually as netlist is a interconnect of gates, you wont usually find any 'assign' statements in it.
Example:

wire w1;
wire w2;
wire w3;

assign w3 = w1 & W2;

So your question what will happen?
w3 will get the vallue of w1 anded with w2.

If you are asking what will happen if assign is present in netlist, the answer is it depends upon the context in which it is being used. If you can cut-paste your netlist containing the 'assign' statement, I will be in more better postition to answer.
kr,
Aviral Mittal.

 

[xv_ning999]

then how to avoid assign statement appearing in our netlist .v file

 

[rogger123]

hi
the bad side of having assign statments in the netlist.
say for example u have a two ports in1 and out1
and they are connected wihtout any logic in between
assign out1 = in1 ;
the above statment is not accepterd by backend tools like encounter etc...
therefore u need to buffer direct input to output connections(feedthrough). this can be done in design compiler of physical compiler using

set_fix_multiple_port_nets -all / -feedthrough

hope this helps
cheers
rogger