xiexi
Member level 4
I found some words in the model file, it says:
$ 2. Bias
$ VDS <= |5|V, VGS <= |5|V, VBS <= |3|V
So I am not sure if I can use use VBS>3V in my design, then I ask foundary and it answer is :
It should judged by bias conditions, for example NMOS
If we add Vgs=5V, then the inversion layer form, and electrons collect near the surface, that means underside hole concentration increase, so the junction concentration increase, it lead Vbs can not add more.
Now I am still confused about their answer, can anyone give me instruction and explain more clearly, thanks.
$ 2. Bias
$ VDS <= |5|V, VGS <= |5|V, VBS <= |3|V
So I am not sure if I can use use VBS>3V in my design, then I ask foundary and it answer is :
It should judged by bias conditions, for example NMOS
If we add Vgs=5V, then the inversion layer form, and electrons collect near the surface, that means underside hole concentration increase, so the junction concentration increase, it lead Vbs can not add more.
Now I am still confused about their answer, can anyone give me instruction and explain more clearly, thanks.