ashik_na
Junior Member level 1
Hi All,
I am designing ADPLL for video applications.
For this ADPLL, I am using DCO as oscillator.
Delay cells are used to generate the oscillation.
But frequency chara ( Freq Vs Code ) of the DCO is not linear.
there is large Δfreq, change at high frequencies for small change in code by comparing with lower frequency side.
For eg - Please see the below table
Code Freq( MHz)
0 530
1 309
2 230
3 181
4 151
5 128
6 112
7 100
8 89
I want to design a linear DCO. What is the possible designs to get the linear frequency chara ?
I am a little confused how these type ADPLL will get locked with this DCO behavior .
Could you Please clarify ?
Thanks in advance..!!
I am designing ADPLL for video applications.
For this ADPLL, I am using DCO as oscillator.
Delay cells are used to generate the oscillation.
But frequency chara ( Freq Vs Code ) of the DCO is not linear.
there is large Δfreq, change at high frequencies for small change in code by comparing with lower frequency side.
For eg - Please see the below table
Code Freq( MHz)
0 530
1 309
2 230
3 181
4 151
5 128
6 112
7 100
8 89
I want to design a linear DCO. What is the possible designs to get the linear frequency chara ?
I am a little confused how these type ADPLL will get locked with this DCO behavior .
Could you Please clarify ?
Thanks in advance..!!