kilone
Member level 1
I want to try NIOSII in my new embedded design. According to Altera's announcement, NIOSII can provide up to 200 DMIPS performance(in coming Stratix2), and we also know that there exist abundant hardware resources inside FPGA devices(Registers, High Speed Buses, IPs, etc.), which will make most dsp algorithms and data exchange operations much more easy to be implemented.
But what about the control sequences(TCP/IP for example)? General Purpose CPU (like Intel Pentium series) usually has much higher clock speed (although operations like MULT may consume up to 100 cycles). If both dsp algorithms and high level protocols will be implemented inside NIOSII, how can I evaluate it?
Does anyone here has related experience please?
But what about the control sequences(TCP/IP for example)? General Purpose CPU (like Intel Pentium series) usually has much higher clock speed (although operations like MULT may consume up to 100 cycles). If both dsp algorithms and high level protocols will be implemented inside NIOSII, how can I evaluate it?
Does anyone here has related experience please?