5 pts for helping me(modelsim problem)

[mamsamae]

i work in an fpga design with ise8.2 and use blockram in it when i try to simulate it in the modelsim the following error message appears

# ** Error: L:/Master/simulation_lib/XilinxCoreLib_ver/XilinxCoreLib_ver_source.v(24639): $recovery( posedge CLKB:3080 ns, posedge CLKA &&& collision_posa_posb:3080 ns, 1 ns );
# Time: 3080 ns Iteration: 4 Instance: /test_module/mac_recsiver/cpu/ram_no_1/inst

 

[echo47]

I'm not sure, but examine your simulation at time = 3080 ns to see if both block RAM ports are writing simultaneously to the same memory address. That would be a "collision" with unpredictable results in hardware, so the the Xilinx HDL model may be warning you.

 

[rberek]

You will also get an error like this even when both ports of the two port RAM are set to the same address and you are writing to only one of them.

The output of the second port will change to the data that you have written on the first port within a clock or two of the write. You have to ensure, by design, that if you are reading the output data within a few clocks of the write on the other port, that you are getting the data you want.

To use your case as an example, at time 3080, you are writing into one port (say port A) of your memory. The address of the other port (port B) is probably the same as the address on port A. Thus if you sample port B at this time, you'll get the old value. A clock or two later, if you sample port B, you'll get the new value. Since there is no read enable on the ports, the simulator doesn't know when you're sampling the data on port B, so it sends out a generic error to make you go look and check out the situation for yourself.

Its your job to coordinate reads and writes between the two ports so you are always getting the data you want.