10% Duty Cycle in VHDL

[missbirdie]

duty cycle vhdl

How can I implement in VHDL a 10% Duty cycle clock from the 50 MHz clock in spartan 3 ??

 

[echo47]

vhdl duty cycle

What frequency output clock do you need?

 

[missbirdie]

writing vhdl code to get 50% duty cycle clock

100 KHz

 

[echo47]

vhdl simulation duty cycle

I'm no good at writing VHDL, but maybe this Verilog module will help you. It's a 10-bit counter that continuously counts up from -50 through +449. The most significant bit is output through a clock buffer, for high fanout and low skew, suitable for clocking other synchronous logic. (I don't know if you really need that buffer.) When the input clock is 50 MHz, the output is a 1us pulse every 10us.

module top (clk, clkout);
  input             clk;    // synthesis attribute PERIOD clk "50 MHz";
  reg signed  [9:0] count=0;
  output            clkout;

  BUFG u1 (.I(count[9]), .O(clkout));  // clock buffer

  always @ (posedge clk)
    count <= count == 449 ? -50 : count + 1;
endmodule

 

[karikalan_t79]

duty-cycle vhdl

use dcm or pll to get the duty cycle change

 

[kyawsoelwin]

what is a duty cycle in a verilog hdl

hey !
check it this symbol and my simulation



tick_max output is 10% duty cycle of any input clock! is it ok??

the VHDL code is as below

Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;

entity M_counter is

generic (N: integer := 4;
M: integer := 10 );
port(
clk, reset: in std_logic;
q : out std_logic_vector ( N-1 downto 0);
max_tick: out std_logic
);
end M_counter;

Architecture arch_M of M_counter is
signal r_reg : unsigned ( N-1 downto 0);
signal r_next : unsigned ( N-1 downto 0);

-- register
begin

process(clk, reset)
begin
if (reset='1')then
r_reg<= (others=>'0');
elsif (clk'event and clk='1')then
r_reg<=r_next;
end if;
end process;

--next state logic

r_next<= (others=>'0') when r_reg = (M-1) else
r_reg+1;

--output logic
q<= std_logic_vector (r_reg);
max_tick <= '1'when r_reg=(M-1) else'0';

end arch_M;