1)connect different clock domains 2)bus arbiter

[Vacuum]

Hello!
I'm developing a system in verilog where modules connected together via shared bus.
Can anyone suggest me the way
1)how to connect modules clocked at different frequences
2)how to realize bus arbitration logic
Many thanks!

 

[sree205]

hope its not too late to answer this question.

1. in the module interface, look for control signals and double flop them to prevent any metastability. Incase of data signals, use FIFO.

2. This is not quite clear. Are you looking for an arbitration mechanism wherein different master's data can be arbitrated and sent along a common bus ?