noiseless
Full Member level 3
In the pipelined ADC, there needs Vref+ and Vref- voltage for the DAC. Because of the large number of stages, the caps load is huge for the reference voltage, which requires buffer for the quick settling. I have two questions about it.
1. All stages share only one reference buffer, or each stage use one. The reason is I concern the settling error caused by mismatch of the clock timing if only share one buffer. Otherwise will consume too many power
2. The reference voltage is usually generated by the transistor ladder. What kind of buffer people is usually used? I do not want to used unit gain buffer, for it high power consumption. Any other methods?
1. All stages share only one reference buffer, or each stage use one. The reason is I concern the settling error caused by mismatch of the clock timing if only share one buffer. Otherwise will consume too many power
2. The reference voltage is usually generated by the transistor ladder. What kind of buffer people is usually used? I do not want to used unit gain buffer, for it high power consumption. Any other methods?