matrixofdynamism
Advanced Member level 2
For clock crossing FIFO why don't the signals empty & full goto both clock domains?
Here is a picture of the Dual Clock FIFO used to "transmit multi-bit signals from one clock domain to another" and it is "usually implemented as a wrapper around a dual port RAM". It is from a book.
It is not clear to me when exactly are the signals full and empty asserted. Why does signal full only goto the "write clock domain" and empty only goto the "read clock domain"?
I mean, the write clock domain may know when to stop writing because of the full signal, but how does it know when to start writing again since it does not get the empty signal?
Similarly, the read clock domain gets the empty signal so it knows when to stop reading, but it does not get the full signal so how does it know when to start reading?
Here is a picture of the Dual Clock FIFO used to "transmit multi-bit signals from one clock domain to another" and it is "usually implemented as a wrapper around a dual port RAM". It is from a book.
It is not clear to me when exactly are the signals full and empty asserted. Why does signal full only goto the "write clock domain" and empty only goto the "read clock domain"?
I mean, the write clock domain may know when to stop writing because of the full signal, but how does it know when to start writing again since it does not get the empty signal?
Similarly, the read clock domain gets the empty signal so it knows when to stop reading, but it does not get the full signal so how does it know when to start reading?