Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

ERROR in cadence while checking DRC rules

Status
Not open for further replies.
S

S_J_K

Newbie level 3
Joined
May 20, 2016
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
26
hello everyone!
i have designed the symbol view of cmos amplifier and now i am creating the layout of it. While checking the DRC rules , error named "tap area" is being observed. Can anyone help me in resolving this error?

regards
SJK
 

It is hard to say anything without more details but "tap area" is related to well/substrate connections. Probably You have not enough or proper bulk connections.
 

#Dominik
I have exported the schematic for layout. Do i have to make layout myself?
 

An auto-generated layout probably has no taps, hence
tap-density type errors. It's telling you "OK, your turn
to step in and finish the job" most likely.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top