Problem with post layout simulation ams 0.35 with pads

hello ,

i have designed a 100 Mhz , 5V ring oscillator using ams 0.35 technology. I added pads and during the schematic simulations phase everything works fine. I did the layout and after post layout simulation using the extracted circuit, my circuit wont oscillate . Does anyone have any idea how to validate lvs and post layout simulation with padring ?

Check the additional parasitic caps in the extracted layout netlist. If you suspect a specific high parasitic cap load (such as the connection between the ring oscillator and the pad), add such a cap to this connection in your schematic, re-simulate and see if you can reproduce this failure. Perhaps you need a buffer in between.

Which PDK version, virtuoso and which tool (Assura, Calibre?) are You using?

Probably You didn't extracted supply nets properly. Check in netlist if number of pins of extracted view is the same as in schematic one, for given blocks.

I usa Assura Virtuoso IC6.1.5-500.13 . The problem is with supply nets =========================================================================[PADS]
====== Matched Instances with Bad Net Connections =============================
===============================================================================

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 1)
Schematic Instance: I139 BU1P_V5
Layout Instance: |I139 BU1P_V5

Pin SchNet : LayNet
--- ------ : ------
gnd5o! gnd! : gnd5r!
vdd3r! vdd! : vdd3r!
vdd5o! vdd! : vdd5o!
vdd5r! vdd! : vdd5r!

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 2)
Schematic Instance: I117 BU1P_V5
Layout Instance: |I117 BU1P_V5

Pin SchNet : LayNet
--- ------ : ------
gnd5o! gnd! : gnd5r!
vdd5o! vdd! : vdd5o!
vdd5r! vdd! : vdd5r!

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 3)
Schematic Instance: I138 BU1P_V5
Layout Instance: |I138 BU1P_V5

Pin SchNet : LayNet
--- ------ : ------
gnd5o! gnd! : gnd5r!
vdd5o! vdd! : vdd5o!
vdd5r! vdd! : vdd5r!

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =(badcon 4)
Schematic Instance: I107 BU1P_V5
Layout Instance: |I107 BU1P_V5

Pin SchNet : LayNet
--- ------ : ------
gnd5o! gnd! : gnd5r!
vdd5o! vdd! : vdd5o!
vdd5r! vdd! : vdd5r!

For any of these (I/O- ?) cells, in schematic its GND pin is connected to gnd5o! , whereas in layout it is connected to gnd5r! .