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Reading stl format in verilog/systemverilog

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dmm

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Does anyone know to read stl(Socket Transaction Language) format file in Verilog/Systemverilog?
 

The problem is reading the ":" after the cycle. I tried to read it using "$fscanf", but only white spaces are readable.
 

Or use an external parser, and make a wrapper using PLI. That would seem a little less painful than doing it all yourself in verilog. Or since you said system verilog, maybe use DPI instead. DPI is less hassle than PLI. But both will still require work on your part. :p The choice of external vs in verilog itself would depend on what you have to parse... Anyways, just suggesting you look into DPI and see if it fits the bill for your use case.
 

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