+ Post New Thread
Results 1 to 4 of 4
  1. #1
    Newbie level 6
    Points: 591, Level: 5

    Join Date
    Jul 2011
    Posts
    12
    Helped
    0 / 0
    Points
    591
    Level
    5

    set_input_delay means ?

    Hi guys,
    I'm confused about set_input_delay in DC. Does it mean the delay from the signal source through the I/O pad to the input port (no matter the port is register's or gate's) ? Or it means the delay from the signal source through the I/O pad to the first stage's register in the design?

    Another question is : if I have two different designed modules A and B, and one output of A is connected to one input of B. What if both output of A and input of B are registered, should the set_input_delay be zero????

    •   Alt6th May 2012, 11:23

      advertising

        
       

  2. #2
    Full Member level 1
    Points: 929, Level: 6

    Join Date
    Apr 2012
    Location
    US
    Posts
    101
    Helped
    24 / 24
    Points
    929
    Level
    6

    Re: set_input_delay means ?

    Quote Originally Posted by sages View Post
    Hi guys,
    I'm confused about set_input_delay in DC. Does it mean the delay from the signal source through the I/O pad to the input port (no matter the port is register's or gate's) ? Or it means the delay from the signal source through the I/O pad to the first stage's register in the design?
    set_input_delay means the delay from signal source (usually clk input of a signal launching flop external to I/O) to the I/O pad

    Quote Originally Posted by sages View Post
    Another question is : if I have two different designed modules A and B, and one output of A is connected to one input of B. What if both output of A and input of B are registered, should the set_input_delay be zero????
    The input delay here will be from clk input of a signal launching flop in A to corresponding input port in design B

    Think of this way, if input delay is not mentioned, then data path time margin is optimistic as in reality some time will be used up in travelling to input port from source of the signal. Without input delay, your design may be passing setup but in reality if input delay is considered it may violate setup in capturing flop.



    •   Alt6th May 2012, 20:22

      advertising

        
       

  3. #3
    Advanced Member level 3
    Points: 8,640, Level: 22
    yadavvlsi's Avatar
    Join Date
    Nov 2010
    Location
    Bangalore, India
    Posts
    957
    Helped
    459 / 459
    Points
    8,640
    Level
    22

    Re: set_input_delay means ?




    •   Alt7th May 2012, 12:24

      advertising

        
       

  4. #4
    Newbie level 6
    Points: 591, Level: 5

    Join Date
    Jul 2011
    Posts
    12
    Helped
    0 / 0
    Points
    591
    Level
    5

    Re: set_input_delay means ?

    Thank U for ur explanation



+ Post New Thread
Please login