set_input_delay dc vs pt

[taepyeong]

Hello I am synthesis chip.

When I use dc,
I used this constraint.

-------------------------
set_input_delay -min 1 [get_ports U_DIGITAL_DUALEDGE_TOP/I_RISE] -clock U_DIGITAL_DUALEDGE_TOP/I_CLK
--------------------------

but when I use thay constraint in primetime.
I got this message.

--------------------------
set_input_delay -min 1 [get_ports U_DIGITAL_DUALEDGE_TOP/I_RISE] -clock U_DIGITAL_DUALEDGE_TOP/I_CLK

Warning: No port objects matched 'U_DIGITAL_DUALEDGE_TOP/I_RISE' (SEL-004)

Error: Nothing matched for ports (SEL-005)
Error: Nothing matched for object_list (SEL-005)
--------------------------

Does it any reason?

In primetime I also set this clock.
even it gives some warning message but it works.

--------------------------
create_clock -period [expr $PERIOD_I_CLK * $clock_margin] [get_pins U_DIGITAL_DUALEDGE_TOP/I_CLK ]

Warning: Creating a clock on internal pin 'U_DIGITAL_DUALEDGE_TOP/I_CLK'. (UITE-130)

Warning: Creating 'clock' on a hierarchical pin 'U_DIGITAL_DUALEDGE_TOP/I_CLK'. (UITE-137)
1
--------------------------

 

[taepyeong]

I used that constraint in DC.
And I extracted sdc from DC.

------------------------------------
set_input_delay -clock U_DIGITAL_DUALEDGE_TOP/I_CLK -min 1 [get_pins U_DIGITAL_DUALEDGE_TOP/I_RISE]
-------------------------------------

And it works at Primetime.

Anyone know?