What does Constant hierarchical Pin(s) means in RTL compiler?

[bardia]

Hi everybody,

When I check the design in RTL compiler 10.1 after synthesis, I get the following summary for my design.

I know that Assigns are not good and should be removed before importing design in SoC encounter and I know how to do it.

But my question is about the Constant hierarchical Pin(s). I don't know what those mean and if they are important? Should they also be removed before place and route? And how?


Name Total
-------------------------------------------
Unresolved References 0
Empty Modules 0
Unloaded Port(s) 0
Unloaded Sequential Pin(s) 0
Assigns 83
Undriven Port(s) 0
Undriven Leaf Pin(s) 0
Undriven hierarchical pin(s) 0
Multidriven Port(s) 0
Multidriven Leaf Pin(s) 0
Multidriven hierarchical Pin(s) 0
Multidriven unloaded net(s) 0
Constant Port(s) 0
Constant Leaf Pin(s) 3
Constant hierarchical Pin(s) 297
Preserved leaf instance(s) 0
Preserved hierarchical instance(s) 0
Libcells with no LEF cell 0
Physical (LEF) cells with no libcell 27

 

[chiranjeevinaidu]

Hi
constant hierarchical pins are either connecting to zero or one....
In synthesized net list those hierarchical pins are connecting to tie Low or tie High ...

(1'b0)
(1'b1)