Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

[SOLVED] Help! VHDL code for 7-segment decoder

Status
Not open for further replies.
N

ngtdat

Newbie level 3
Joined
Feb 25, 2012
Messages
4
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,305
Hi all,
I just made a vhdl code for my 7-segment decoders and here is my code:
Code: 
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

entity char_seg7 is
	port(a,b,c,d: in std_logic;
		 hex: out std_logic_vector(0 to 6));
end char_seg7;

architecture char_seg7 of char_seg7 is
begin
	process (a,b,c,d)
		begin
			case "abcd" is
				when "0000" => hex <= "0000001";
				when "0001" => hex <= "1001111";
				when "0010" => hex <= "0010010";
				when "0011" => hex <= "0000110";
				when "0100" => hex <= "1001100";
				when "0101" => hex <= "0100100";
				when "0110" => hex <= "0100000";
				when "0111" => hex <= "0001111";
				when "1000" => hex <= "0000000";
				when "1001" => hex <= "0000100";
				when others => hex <= "1111111";
			end case;
	end process;
end char_seg7;

when i complied the code, it seemed OK but when i put it in model sim and simulate, the results are not as i expect

can anyone tell me what i was wrong :(
 

whats not as expected? Please be more specific with your questions.

---------- Post added at 10:59 ---------- Previous post was at 10:58 ----------

Just looking, "abcd" is a string, and has nothing to do with the inputs, so the output will always be "1111111"

you need:

case a&b&c&d is..
 

TrickyDicky said:
whats not as expected? Please be more specific with your questions.

---------- Post added at 10:59 ---------- Previous post was at 10:58 ----------

Just looking, "abcd" is a string, and has nothing to do with the inputs, so the output will always be "1111111"

you need:

case a&b&c&d is..
Click to expand...

i tried, but got this error:

Error (10327): VHDL error at lab2_part2.vhd(103): can't determine definition of operator ""&"" -- found 2 possible definitions

:-(
 

This compiles, but I can't explain the error:

Code: 
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;

entity char_seg7 is
	port(a,b,c,d: in std_logic;
		 hex: out std_logic_vector(0 to 6));
end char_seg7;

architecture char_seg7 of char_seg7 is
begin
  process (a,b,c,d)
    variable tmp_vector: std_logic_vector(3 downto 0);
    begin
      tmp_vector := a&b&c&d;
      case tmp_vector is
        when "0000" => hex <= "0000001";
        when "0001" => hex <= "1001111";
        when "0010" => hex <= "0010010";
        when "0011" => hex <= "0000110";
        when "0100" => hex <= "1001100";
        when "0101" => hex <= "0100100";
        when "0110" => hex <= "0100000";
        when "0111" => hex <= "0001111";
        when "1000" => hex <= "0000000";
        when "1001" => hex <= "0000100";
        when others => hex <= "1111111";
     end case;
  end process;
end char_seg7;

I really want to know why there is a type error without the temporary variable. For some reason, it can't distinguish between std_logic_vector and std_ulogic_vector when the concatenation is done directly in the case statement. If you concatenate std_logic, then the result must be std_logic_vector?
 

IIRC, in VHDL 2008 Std_logic_vector is actually a subtype of std_ulogic_vector, to help with all the silly problems there were differentiating between the two.
 

It seems that when individual bits of type std_logic and std_ulogic are concatenated (in any combination) the result can be std_logic_vector or std_ulogic_vector.
It is no problem to use such an expression in an assignment, since the target type is known.
The case statement has no expected target type, so the compiler doesn't know what type the result should have.

This problem can not happen if std_logic or std_ulogic is concatenated to std_ulogic_vector or std_logic_vector because the result will have the same type as the input vector.
In that case, the type of the single input bits doesn't matter. The input vector and the concatenated output will always have the same type.

This also means that it is impossible to concatenate std_logic_vector with std_ulogic_vector. One of them must be casted.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top