manrajgujral
Junior Member level 1
View attachment LowPass Butterworth filter_msg1g10.pdf
I recently worked on Cadence Layout XL where my task was to design a butterworth filter to match a specification using ASIC Process.I started with CMOS level schematic - to testing the schematic - extracting it to form an extracted Op-Amp - using the Op-Amp to make an 8th order butterworth filter. (and to extract the filter in the end and check it) though I have submitted the report , but there are few things that bothered me that I couldnt put :
1. I couldn't show the step by step procedure in using Cadence AMS HIT-Kit. but then again. the whole thing wasn't possible to include it in a 2500 words report anyway.I only showed few thing those were imp.
2. I didn't show any calculations i had done form my Filter design, then again the purpose of the report was to be aware of the Process involved in an ASIC methodology.
3. Though i took me almost 2 weeks to make the IC layout (extracted) from scratch, i had to finish the report in 1 day ,therefore, a lot of mistakes - sentence formation- "formal"ness of a report etc
This being my 1st IEEE format report, I would like to know what you guys think could be done better. I "will" have to write a lot more reports on different topics (and i am writing one more now - due in a weeks time), I could use some suggestions , specially on the content (yes i have seen the IEEE Papers online and thats how i started my paper as well)
PS: don't copy though.
I recently worked on Cadence Layout XL where my task was to design a butterworth filter to match a specification using ASIC Process.I started with CMOS level schematic - to testing the schematic - extracting it to form an extracted Op-Amp - using the Op-Amp to make an 8th order butterworth filter. (and to extract the filter in the end and check it) though I have submitted the report , but there are few things that bothered me that I couldnt put :
1. I couldn't show the step by step procedure in using Cadence AMS HIT-Kit. but then again. the whole thing wasn't possible to include it in a 2500 words report anyway.I only showed few thing those were imp.
2. I didn't show any calculations i had done form my Filter design, then again the purpose of the report was to be aware of the Process involved in an ASIC methodology.
3. Though i took me almost 2 weeks to make the IC layout (extracted) from scratch, i had to finish the report in 1 day ,therefore, a lot of mistakes - sentence formation- "formal"ness of a report etc
This being my 1st IEEE format report, I would like to know what you guys think could be done better. I "will" have to write a lot more reports on different topics (and i am writing one more now - due in a weeks time), I could use some suggestions , specially on the content (yes i have seen the IEEE Papers online and thats how i started my paper as well)
PS: don't copy though.