lhlbluesky
Banned
jitter problem
i designed a voltage reference,as the figure shows;
but when i simulate, i find that the voltage vref which is generatd by PTAT jittered
with very large amplitude,and settles very slowly;
figure2 is the wave,very strange;if vref settles slowly,then vcm settles more slowly,and the whole circuit doesn't work well;
how to solve this problem;pls give me some advice,thanks all.
i designed a voltage reference,as the figure shows;
but when i simulate, i find that the voltage vref which is generatd by PTAT jittered
with very large amplitude,and settles very slowly;
figure2 is the wave,very strange;if vref settles slowly,then vcm settles more slowly,and the whole circuit doesn't work well;
how to solve this problem;pls give me some advice,thanks all.