Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Source Latency from external clock source and PLL

Status
Not open for further replies.
P

praneshcn

Member level 5
Joined
Aug 23, 2007
Messages
90
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,899
Hi,

when we have an external clock source and an PLL inside a chip level design from which point to which point will source latency be considered. As it is a chip level design consider the clock pad in between the external clock source and PLL.
 

Re: Source Latency

To my understanding,

if the clock is from,
External Clock Pin(Say IO pin) ----> PLL ----> Clock Generation Point
Source Latency is from PLL output to Clock Generation Point

For other cases like below
External Clock Pin -----> Clock Generation Point
Source Latency is from IO pin to Clock Reaching point/Generation point

can anyone put your comments on this.
 

Source Latency

This sounds more like you have two clock sources and they are either selectable, or they drive different clocks on the chip. If they are two different clocks then you need to specify both source latencies as stated by vikramc98406. If the clocks are selectable, then you need to create two SDC files and select one clock or the other and set the source latency as specified by vikramc98406.
 

Re: Source Latency

source latency=source(oscillator) to clk defination pin(chip clk pin)
network latency=clkpin(port def)to flop clk pin
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top