viyaaloth
Junior Member level 3
Hi All,
I am planning to use AXI4-Stream interface as a standard interface for inter IP communication(between two IPs) with in FPGA. one IP is ADC IP which forwards samples from ADC IC to DAQ IP. second IP is DAQ IP(data acquisition IP) which gathers all samples from ADC IP. Transaction is initiated by DAQ IP.So DAQ IP must be master in my design. And it is accepting data from slave ADC IP.
But I am having a doubt that whether AXi-Stream master will capable of reading data(from slave ADC IP).
If we are considering the axi-stream master example template from xilinx,master will send(write data to slave) data not reading/receiving data.
.
Any suggestion/reply would be appreciated .
I am planning to use AXI4-Stream interface as a standard interface for inter IP communication(between two IPs) with in FPGA. one IP is ADC IP which forwards samples from ADC IC to DAQ IP. second IP is DAQ IP(data acquisition IP) which gathers all samples from ADC IP. Transaction is initiated by DAQ IP.So DAQ IP must be master in my design. And it is accepting data from slave ADC IP.
But I am having a doubt that whether AXi-Stream master will capable of reading data(from slave ADC IP).
If we are considering the axi-stream master example template from xilinx,master will send(write data to slave) data not reading/receiving data.
.
Any suggestion/reply would be appreciated .