Binome
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Hi,
I'm simulating a vhdl design in questasim. One of the signals is deleted when optimization is used and I'd like to understand why.
This signal is directly connected to an output of the simulated component and I can see it changing when simulating with no optimization. Is there a detailed report explaining why it is deleted?
Thank you for any help.
I'm simulating a vhdl design in questasim. One of the signals is deleted when optimization is used and I'd like to understand why.
This signal is directly connected to an output of the simulated component and I can see it changing when simulating with no optimization. Is there a detailed report explaining why it is deleted?
Thank you for any help.