pcmistic
Newbie level 2
Hi, I'm quite newbie in Verilog and FPGAs. I'm trying to access the DDR2 SDRAM on my FPGA board (Opal Kelly XEM6310-LX45). I instantiated RAM controller module which i generated with MIG tool in ISE. Now I'm trying to control the interface. I have read UG388 but there is a point that I'm confusing. Does MIG module have Write, Read and Command FIFOs internally, or do I add these FIFOs to MIG externally?