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AXI EMC v3.0 IP core

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Sunayana Chakradhar

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Hello,

I plan to use the AXI EMC v3.0 IP to interface my asynchronous SRAM to the zynq 7020. I will be using the EMIO pins on the PL as all my MIO pins have been exhausted. I have 2 questions

1) Where do I find the exact EMIO pin numbers? Is there a tool which can help me with this?
2) The SRAM module which I am using is 70V24L15PFG which has 16 I/O lines and 13 address lines. Apart from this there is semaphore, busy, interrupt, byte enable, output enable lines. The AXI EMC v3.0 IP core doesn't provide the extra lines like semaphore, busy etc. SO I should be writing a HDL code for these extra lines and then integrating it with the AXI EMC v3.0 IP core. I want to know if this will be possible and how should I be doing it?

Thanks
 

I haven't used a Zynq, but browsing the Technical Reference Manual, it seems you are doing the wrong thing.

Use the SMC on the MIO (as that is the only interface it's allowed) and move all the other signals peripherals to the EMIO.

Or you should be using the PS-PL AXI Interfaces (which are not EMIO or MIO) to use the AXI EMC v3.0 IP, this means you can use any other PL pin besides the EMIO and MIO pins.

At least this looks to be the case from the limited 10 minutes of reading I've done.
 

Thanks for your reply. I have one QSPI flash and one external SRAM shared memory. I have connected the QSPI on the PS using dedicated SRAM/ NOR flash interface. I am confused as to where I need to connect the SRAM as the QSPI/ Nor flash interface can support only one type of memory connection.
 

is there a reason for the external shared memory? eg, could you replace it with the on-chip memory of the Zynq?
 

I need to establissh communication between imx6 processsor any zynq 7020 using shared memory concept.
 
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