Sunayana Chakradhar
Member level 5
Hello,
I plan to use the AXI EMC v3.0 IP to interface my asynchronous SRAM to the zynq 7020. I will be using the EMIO pins on the PL as all my MIO pins have been exhausted. I have 2 questions
1) Where do I find the exact EMIO pin numbers? Is there a tool which can help me with this?
2) The SRAM module which I am using is 70V24L15PFG which has 16 I/O lines and 13 address lines. Apart from this there is semaphore, busy, interrupt, byte enable, output enable lines. The AXI EMC v3.0 IP core doesn't provide the extra lines like semaphore, busy etc. SO I should be writing a HDL code for these extra lines and then integrating it with the AXI EMC v3.0 IP core. I want to know if this will be possible and how should I be doing it?
Thanks
I plan to use the AXI EMC v3.0 IP to interface my asynchronous SRAM to the zynq 7020. I will be using the EMIO pins on the PL as all my MIO pins have been exhausted. I have 2 questions
1) Where do I find the exact EMIO pin numbers? Is there a tool which can help me with this?
2) The SRAM module which I am using is 70V24L15PFG which has 16 I/O lines and 13 address lines. Apart from this there is semaphore, busy, interrupt, byte enable, output enable lines. The AXI EMC v3.0 IP core doesn't provide the extra lines like semaphore, busy etc. SO I should be writing a HDL code for these extra lines and then integrating it with the AXI EMC v3.0 IP core. I want to know if this will be possible and how should I be doing it?
Thanks