Connecting modules in VHDL

I created 3 modules namely PGA, ADC, DAC in 3 different folders and simulated and verified them successfully. Each of the three has 4 or 5 other sub-modules..

I now need to create a TOP module that connects to all the 3 modules and also their respective submodules, in this case the name of the folder is Analog_Capture.

When I use a normal port mapping it doesnt work. I think it is because they are in differnt work directory and folders.

Shown are the pictures

The first image is what I get in ISE after connecting the all three top modules but their sub modules are not referenced.


Second image shows my folder structure.


Third image shows sub-modules in one of the modules named PGA.
.

I am not sure if I should use a package or manually add each of the files individually to the project window in ISE. Need help in referencing them. Thank you in advance

You need to either add all the files to the project using the menu item "add source files" (or something like that), or another option is to add search directories to your project for those sub module source files.

Regards

@ads-ee thank you. it works. however, can these sub modules be included in packages and the package (for ex. 'work.my_pkg.all') be called instead?

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the reason why I am asking this is, in some cases I may have a project in C: drive and other project in D: drive or may be in the shared drive (which could be a a colleagues work). In these cases I wish to somehow use the existing work from like a library. So how do I do that ? I am not understanding if package will be a solution for this. Ideas please. Regards.

Packages contain subprograms (functions, procedures), type definitions and constants, not modules.

I think there are good reasons to keep all project files in a (possibly hierachical) directory structure. So the project can be easily copied, archived or managed by version control software.

sorry misunderstood sub programs for sub modules.... anyways wasted/spent time to learn this.. will do as you suggested

thank you both @ads-ee and @FvM