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Parastics effect on Bootstrapped S&H

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Ravinder487

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Hi all,
will the parasitics at node 1(in the schematic attached) effect the linearity of sample and hold or the parasitics at node2 effect?
 

I am not sure but the node 2 parasitics are mainly dominant by gate of transistors.So it should have more effect on circuit non-linerity.
 

but node 2 is driven by PMOS transistor,as it seems to me,even though there are parasitics it will try to charge node 2 potential to potential at node 1.
Please respond immediately....!!
 

It seems But at node 1 we can adjust value of capacitor Cb to cancel parasitic effect of node 1.
 

parasitic effect can be minimized by increasing the value of capacitor Cb but can't be eliminated completely.My question is if the value of Cb is fixed due to speed consideration then parasitics at which node(1 or 2) will determine gain error of this S&H
 

Ravinder487 said:
parasitic effect can be minimized by increasing the value of capacitor Cb but can't be eliminated completely.My question is if the value of Cb is fixed due to speed consideration then parasitics at which node(1 or 2) will determine gain error of this S&H
Click to expand...
Now if you talk about Cb value then,I think Cb is hold capacitor here.You need to choose it's value very carefully.Then you are right that node 1 parasitic capacitance effect more because cb remember it's previous effect by internal parasitic capacitance at node 1.And i guess hold capacitor is key concern in gain error.
I hope this helps!!!
 
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