Periphery of drain/source

Hi, in the 45nm technology for the NMOS with W=90nm and L=50nm the area of the drain is = 105nm X 90 nm and periphery=2*105nm+90nm is it right?

but when we extract the netlist from the layout it show the PD=2*(105nm+90nm) so which formula is correct?

I think for calculating the the capacitance we do not take the cap. due to the wall of drain which is adjacent to the gate poly.

Please let me know what is the right formula.

Thanks
Tanmay

My teacher once told us to use the formula PD=2*L+W to calculate the periphery, but maybe it is process dependent

The periphery of the drain is 2*(105nm+90nm), but, e.g. when calculating parasitic capacitances, the 90nm side on the side of the channel is not taken into account because there exists the depletion region under the channel and thus there is no sidewall parasitic capacitance on that side.

Thanks.... but still my doubt is that when I extract the netlist from layout the generated pex.netlist file shows the PD and PS as 2*(L+W). So if I simulate that netlist then wouldn't HSPICE consider wrong capacitance? bcoz it will see PD & PS as 2*(L+W) instead of 2*L+W and it will calculate the cap. according to generated PD/PS.

Hmm.. From what I know the PD is 2*L+W, where L and W are the lengths and width of the active region of source/drain. And that is what the extraction shows in Cadence using 90nm.

So i discovered a bug for 45nm??

I do not have enough experience to say if it is a bug or not. What I do think is that the parameters depend on the simulation model. One can probably get the same simulation results with both PD=2*(W+L) and PD=2*W+L dependign on simulation models. So I think it is just a matter of definition.

saruman1983 wrote that the side of the channel is not taken into account because there exists the depletion region under the channel and thus there is no sidewall parasitic capacitance on that side.

Correct me if I am wrong, but I thought the extraction did not take depletion region into account since the depletion region is formed during operation. Furthermore, I also thought there allways was some paracitic capacitance in a pn junction when unbiased. (??)

That is totally correct.
Maybe this particular parasitic capacitance is taken or not taken into accout depending on the region of operation, i don't know (Yarrow thanks for the comment, most helpful).