Gate-source connected MOSFETs for voltage division

[Arnab1233]

Currently, I am engaged in the design of a Thermal Shutdown circuit for an LDO regulator. In this endeavor, I have obtained a circuit schematic from a senior colleague, which utilizes three NMOS transistors configured as voltage dividers.

This particular arrangement is employed due to the minimal current flow observed across the branch, which is on the order of picoamperes.

I have provided an attached image of the schematic for reference. Subsequently, I conducted simulations and confirmed the circuit's satisfactory performance.

However, I am now seeking a mathematical approach to determine the aspect ratio of the transistors and the resulting resistance offered by the MOSFETs, as they operate in cut-off mode.

Unfortunately, I have been unable to locate a suitable formula that elucidates the resistance of a MOSFET in cut-off or subthreshold conditions, including the role of non-zero body-source voltage of the upper two MOSFETs.

 

[dick_freebird]

Yeah, that's not good - not only are you working off leakage
(maybe the subthreshold slope leaves you at some channel current
besides diode Is, or maybe not - down to process details). But the
varying body effect is liable to be a strong mismatch term.

Are you sure that maybe M19 wasn't supposed to be PMOS?
With body tied appropriately of course. "vnp" is a hint perhaps.
And think about M20 too, with a lot of L?

Maybe you want to take a step back and pencil out the desired
operation, to guide you as you hook it up.