tanmayshah
Newbie level 5
Hi, in the 45nm technology for the NMOS with W=90nm and L=50nm the area of the drain is = 105nm X 90 nm and periphery=2*105nm+90nm is it right?
but when we extract the netlist from the layout it show the PD=2*(105nm+90nm) so which formula is correct?
I think for calculating the the capacitance we do not take the cap. due to the wall of drain which is adjacent to the gate poly.
Please let me know what is the right formula.
Thanks
Tanmay
but when we extract the netlist from the layout it show the PD=2*(105nm+90nm) so which formula is correct?
I think for calculating the the capacitance we do not take the cap. due to the wall of drain which is adjacent to the gate poly.
Please let me know what is the right formula.
Thanks
Tanmay