role of optocoupler for biasing drain of amplifiers

MIssing VDD supply for UCC5304 opto-isolated gate driver.

The circuit purpose isn't clear. Do you need fast rising RF amplifier drain supply? Why? If you just want to establish a safe power supply sequence for the amplifier, but have e.g. microseconds to milliseconds rise time requirement, a much simpler circuit could be used.

Hello FVM, full schematics with all details related to optocoupler.
Thanks.

Where does UCC5340 VDD come from? It needs a floating voltage supply.

Hello , ucc5304dwvr is a gate driver.The mosfet is a N channel which has conditions for operating.

mosfet source is connected to VSS1 which is ground for secondary side by definition of the datasheet.
The gate of the mosfet is connected to the out of the driver.
what is the logic of the floating voltage here?
why Vss1 which is a ground in datasheet shown bellow is 24V?
Thanks.


https://www.onsemi.com/pdf/datasheet/ndt3055l-d.pdf
https://www.ti.com/lit/ds/symlink/u...939&ref_url=https%3A%2F%2Fwww.mouser.co.il%2F

What do you mean with "Vss1 (...) is 24V"?

Hi,

FvM now twice asked about UCC5304_VDD. Why don´t you give clear informations?
Your schematic in this regard is either wrong or incomplete.

You may ignore forum comments .. but the driver won´t work as long as you don´t apply correct VDD with respect to VSS.
Again: we don´t see this in your schematic.

Klaus

Hello Klaus, Sorry for the missundertanding.
Two extended schematics photos are attached the node is call VIZ and GIZ and its connected to DB02S2415A component as shown in another picture .
mosfter is opened and closed by the Vgs>Vt condition, however what i have inner logical conflict when on one hand we put "floating" Ground.
But on the other hand we the source is not connected to ground it could be connected to power amplifier and the draing of power amplifier is the load and not plain ground.
So how this virtual ground helps us here?
Thanks.

https://www.mouser.co.il/datasheet/2/632/DS_DB02S_D-3106392.pdf

Hi,

In other places you used symbols for power supply. Why not here. It´s almost invisible.
In other places you used meaningful lables like "24V". Why not here?

So to validate your schematic we have to do an internet search for the datsheet of the "DB02S2415A" device. (no link)
It tells it´s a DCDC converter (impossible to see this from the schematic symbol).

It says
* nominally15V output
* nominally 24V input.
While you have 24V available you use +24V and -12V which makes 36V in total. This is the absolute maximum specified. Why?

****

yefj said:

however what i have inner logical conflict when on one hand we put "floating" Ground.

Click to expand...

In electronic circuits the name "GROUND" is a synonym for "(supply) voltage reference".
In a real circuit this is where you connect the black wire of your DVM.

Other names for GROUND are "GND", "0V", "COM" ... there is no perfect name.

In your case you have an isolated system, thus you have a "reference node" at each side of the isolation.
When you use a voltmeter to check the output voltage of the DCDC converter you connect the black wire to "-OUT" or wht you call "GIZ" (whatever that means):
In your circuit this is the HIGH_SIDE_DRIVER_SUPPLY_VOLTAGE_REFERENCE. Not a nice name for a node .. and rather lengthy.

More suitable names would be "HS_GND" for high side ground. or "HS_0V".
And for sure VIZ could then be replaced with "HS_15V" ...

VIZ and GIZ are technically not wrong. You will have you reason why you´ve chosen this names ... but when posting in an international forum we miss some information.

And yes, GIZ is not GND in your case. But the point is it is used to control the MOSFET. And the MOSFET is controlled by V_GS (not by V_G!).
V_GS means the voltage of GATE referenced to SOURCE. SOURCE is the voltage reference. And a voltage reference - as said earlier - is often named "GROUND".

Indeed this [15V_supply, the gate driver, the MOSFET and the according resistors and capacitors] has to be seen as "an isolated unit". Not involved in this unit is what in your schematic is called "GND".

Klaus

Hello Klaus, regarding what you said below.
Yes i understand that we Vgs meand gate in a reference to source pin .
The source PIN is the Giz which is -Vout of DB2S2415A.


my problem starts with the J4 pin shown below.
its suppused to go to the drain of TGA2590 power amplifier.
Why whould the current flow into the TGA2590 at all if our reference ground is located at a tottaly other place.
My TGA2590 will be out of current if we put reference voltage .

We have Giz reference and the GND reference and its confusing the logic
if you could please clarify this point?



"And yes, GIZ is not GND in your case. But the point is it is used to control the MOSFET. And the MOSFET is controlled by V_GS (not by V_G!).
V_GS means the voltage of GATE referenced to SOURCE. SOURCE is the voltage reference. And a voltage reference - as said earlier - is often named "GROUND"."

Hello Klaus,Also this is a very important point could you please point where do thisschematics use 36V? (its not logical too)

It says
* nominally15V output
* nominally 24V input.
While you have 24V available you use +24V and -12V which makes 36V in total. This is the absolute maximum specified. Why?

*****************************************************************

UPDATE:

Yes you are absolutely correct there is something odd in this schematics.
We have 24V and -12V which is 36V difference. in and out Viz and Giz nodes

yefj said:

its suppused to go to the drain of TGA2590 power amplifier.

Click to expand...

If you want to talk about TGA amplifier, then show the circuit.

****

yefj said:

Why whould the current flow into the TGA2590 at all if our reference ground is located at a tottaly other place.
My TGA2590 will be out of current if we put reference voltage .

Click to expand...

Which current, which path, which reference are you talking about?

Klaus

Hello Klaus,I imagine the path of the current as shown in the red arrow.
J4 has tottaly other reference "GROUND" ,J4 is supposed to be the connection to the drain of TGA2590 amplifier.
You are tottaly correct that i miss schematics data and i will try to find it.
But this is tottaly new to me that i have two reference points of GND, one for the MOSFET and one for the power amplifier.
How they play together?what is the logic in doing that?
Thanks.

Hi,

yefj said:

,I imagine the path of the current as shown in the red arrow.

Click to expand...

I already asked: Which current, which path, which reference are you talking about?

The red arrow is what? It begins in unknown space and ends maybe in the GIZ node.

Current does not flow from A to B it flows in a loop. And in a schematic it is along the traces and through devices.

*******
A MOSFET as a switch operates similar to a relay:
If you ignore drive current and swithcing times, it comes rather close to this relay circuit:



Klaus

"Ground" for EE's means 0V. That 0V could be floating or not or tied to PE Gnd or not. But each GND will always have some voltage difference depending on the current and impedance between them. Some designs can tolerate 100mV of noise on Gnd others less. Your growing expertise in this will be measured by the quality of your captured waveforms matching your expectations. Your goal is to create textbook waveforms by careful design.

It depends on your design tolerance of each circuit to GND shift (DC+noise). Logic has the highest noise tolerance here. The FET signal for Vgs Ids
has the lowest tolerance to Gnd noise.
0V

The main purpose of this chip is to prevent this shift which will affect the quality of each switch operation. But putting the high-power Nch TGA2590-CP which operates from 6-12GHz on a remote cable connection create EMI problems for this mismatched transmission line and the transition power loss of the remote FET going from high Vds to low Vds with a high current step pulse.



Therefore I strongly urge you to reconsider your plan and follow the datasheet. That means place your drivers RIGHT NEXT TO the TGA2590 QUORVO chip with an isolated supply and send the TTL-compatible logic signal with an impedance-matched Rin from your logic source (<25 ohm typ for 3.6V logic family) then send that to the connector to cable instead. Then use two different ground symbols to mean that each "ground" is 0V for its circuit function and probe reference. Since you intend to use this switch in the 6-12GHz range, it depends on all signals sharing that ground creating a common mode situation of potential interference between the OUTH current loop with Vss and Gnd reference of the 10 GHz signals.

Isolation is a key tool to minimize EMI problems down the road followed by shielding, filtering as well as careful ground impedance and PDN routing design. Keep in mind , that isolated DC supplies will have feed-thru capacitance and thus a Vcm potential issue. This is often mitigated with a better DC BALUN with shunt Y caps to PE earth (RF CM choke), RF beads on the logic etc.

I have found all HDD designs use this method of feeding logic levels to the R/W chip closest to the magnetic signals chip for flawless RF switching with power-fail write protection and a clean logic level interface using flex PC strips. Many new FET SSR's (solid-state relays) now use this ideology of an RF-modulated gate drive at AC ZCS via a tiny RF cap rather than an optoisolated logic input, even if the package module shows one in a block diagram on the case. ... and this isn't even switching RF signals.

So please reconsider moving TGA2590, M1 etc to the TGA2590 RF board.

This ends my sermon (LOL) for the logic of an isolated FET driver design. Good Luck

Hello ,I am used to this of voltages always with reference to some poing gnd.
When we want to mosfet to be ON we have to put at least 10V Vgs.
we have DB02S2415A which gets as input 24V and -12V while the output is Viz and Giz which are refrenced to gnd of the supply of the component.
Then those two voltage are connected to the UCC5304 out and VSS1.
what is the logic of connecting the output of the DB02S2415A to the output of the UCC5304?
Is it a logical error in the schematics or there is some logic for doing this?
Thanks.



*******************************************
UPDATE:
My GND reference point of the UCC5304 is basicly the gnd of the DB02S2415A .
Given the datasheet shwon below how do i know what voltages will come out of pin7 OUT and pin 5 GND?

You have used symbol for the DB02S2415A with pin numbers in a clockwise position.
(illogical, unless looking at parts from the bottom)

The converter is DC isolated up to 500V but not AC isolated due to 420 pF max.

It is logical to choose -Vin and +Vout = 0V ground to obtain a negative DC out.

But your logic diagram does not clearly communicate what this part's function and raises alot of unnecessary simple questions.

Yes you have chosen the maximum input voltage for no obvious reason 24 - (-12V) = 36 V input and a DC floating output, with high ac coupling. capacitance.

A good schematic will have notes to show assumptions not clear in the logic diagram and can be easily read by any engineer. Go look at some Tektronix or Panasonic schematics to learn how to better schematics better.

Your question title assumes this isolation is optical rather than a modulated RF carrier coupled by xxx pF capacitance, then demodulated to recover the pulses and you wondered about the logic of this. I am assuming it has the required bandwidth you need and that the isolated DC power supply also has minimal pF to mitigate crosstalk from primary to secondary common mode noise converted to differential noise.

I hope my previous rant explains why isolation is useful and why it should be placed close to the load which is analog and more sensitive to parasitic L and C effects on the transition power of a 300W FET. I have not analyzed if the said DCDC converter is adequate for the job of RF isolation as given.

It is always important to include all the impedance assumptions from source path to load, PDN design, shielding, filtering spectral impedance, and isolation all together when dealing with RF, especially 10 GHz.

The Quorvo App Note recommends this load for switched DC = Vg and RF injection at J1, both of which have a very specific spectral impedance to combine for the GATE. Modeling the s-parameters for this may be useful with parasitics included nH/mm & pF/mm or controlled impedance in your planned layout.

I was asking about the reason for making the driver so fast and got no answer yet. Referring to TGA2590 datasheet, the load connected to J4 would be Vd terminal and GND of below circuit. Respectively we have at least 0.2 uF load capacitance. It makes no sense to plan a Vd rate of > 1 to maximal 10 V/us. Depending on the application, 1 V/ms would be sufficient. We didn't yet hear a reason for fast switching.

But even 10 V/us can be achieved with a much simpler circuit, e.g. a PMOSFET driven by a level converter or an integrated automotive high-side smart switch.

Used DC/DC has in fact large isolation capacitance, but it's parallel connected to 0.2 uF load, so involving no actual problem.

Hello , I am just learning the principles of the circuit so i could simulate and understand how it works.
I have two questions:
1.What is the exact voltage of -Vout(Viz) and +Vout(Giz) given the data sheet. In the photo shown below they say 15V but its not enough because i need to know the potential -Vout(Viz) and +Vout(Giz)?




point 2:
There is this boot strap here ,could you give an intuition regarding how this diode and capacitor play together?

Giz is identical with switched output voltage, swinging between 0 and +24V. Viz = Giz + 15V.

Diode 0Du1 isn't related to bootstrap. It's to speed up gate discharge. I believe it has been copied from an UCC5340 application and has no relevance for this circuit.