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[SOLVED] Is it possible to simulate a Qsys design with a Nios II in ModelSim

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matrixofdynamism

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A Nios II design would usually have this softcore with a prgram written in C language connected to a number of peripherals. When we click on generate a top level entity file is generated for us to instantiate whole Qsys system.

Is it possible to simulate Qsys system with a softcore in it? I am asking since the actual instructions for the appliation shall be written in C and thus it is not clear how this shall play out in a testbench where the stimulus is created using HDL or some other language.
 

matrixofdynamism said:
Is it possible to simulate Qsys system with a softcore in it? I am asking since the actual instructions for the appliation shall be written in C and thus it is not clear how this shall play out in a testbench where the stimulus is created using HDL or some other language.
Click to expand...
Yes you can simulate it. You're forgetting that the 'C' code gets compiled into binary object code which then gets loaded into memory. Presumably there must be some PROM device either external to or internal to your FPGA. Load your compiled C code into that model. Give it a clock and let go of reset and the model should take off fetching and executing instructions from memory.

Kevin Jennings
 
I see. Besides this, if a person is developing an IP to be linked with Avalon-MM or Avalon-ST interface, how would they write the testbench for it? I mean are there some tools that facilitate writing testbench for such IP?

I have something called BFM in Qsys for Avalon interfaces as well as some communication protocols. Are they used for this purpose?
 

matrixofdynamism said:
I have something called BFM in Qsys for Avalon interfaces as well as some communication protocols. Are they used for this purpose?
Click to expand...
BFM stands for Bus Functional Model, i.e. a model to test the functionality of a bus. So yes that is what they are used for and if there isn't a BFM for something you write your own BFM to test your code.
 
a BFM is for simulation only. Usually it interfaces to the bus in the normal way, but you control data into and out of the BFM via a more abtract method - eg. push in a large array that then gets played out over the AVST interface with random delays between bursts, to model the behaviour of a real system.

BFMs usually look more like software than standard RTL code.

- - - Updated - - -

as a quick example, heres what some memory controller BFM might look like:

Code VHDL - [expand]
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procedure do_read is
begin
    cs    <= '1';
    rd_en <= '1';
    wr_en <= '0';
    
    wait until rising_edge(clk) and ack = '1' for 6*CLK_PERIOD;
    
    assert( ack = '1' ) report "BUS HUNG!" severity failure;
    
    cs    <= '0';
    rd_en <= '0';
    report "data read was " & to_hstring(data);
end procedure do_read;
 
procedure do_write(d : std_logic_vector(7 downto 0) ) is
begin
    cs      <= '1';
    wr_en   <= '1';
    data_wr <= d;
    
    wait until rising_edge(clk);
    wr_en   <= '0';
    cs      <= '0';
end procedure;
 
 
data_control_proc : process
begin
    do_read;
    
    wait_for_clks(100);
    do_write(x"bc");
    
    wait_for_clks(200);
    report "END OF TEST" severity failure;
end process;
 
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