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the distance between two macros is depends upon the macro pins .
example: if one macro having 20 pins, another macro having 15 pins and your design metal layers are 6
three layers are horizontal and three layers are vertical . so between two macors only route either vertical or horizontal.
metal width is 0.14 spacing is required between two macros 35*0.14/3
Well chiranjeevinaidu in your case you expect the macro is block over all metal layers? Because in general the memories macro are block up metal3 and ROM up metal4, then the router could route over themacroand only minimum space to respect the DRC is required between two macros.
And after you should need to increased the space a lot of wire need to go from one side to other side of macro.
it is called "halo" as to space between two macros. it depends on routing resources that you have and the number of signals that you to route. There have been attempts to design the hardmacro's in such a way that they are abut table(memories are one example) but it is less possible in the newer technologies
For routing resources , your (chiranjeevinaidu) explanation is correct....
Suppose I have to place the buffers in between the macros.
How to accumulate this space.
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