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Re: die size estimation
I think you should have knowledge on :
1. gate counts of the design
2. Memory size
3. I/O
4. Power ring
5. Power strap
and (1+2+3+4+5)/70%= rough die size
Re: fomality problem
You must pay attention to the constant register that be removed by DC. The removed registers may cause many failing points, but in the module level it is easy for the tool to analysis RTL code and no error occurs
CPLD's route resource are all global resource , can garentee the delay , but have the resouce is limited
FPGA has two kinds of route resource, local and global.
Re: question about cts
it is determined by you register number. if one stage clock buffer can drive 12 clock buffer node, you can computer how many stages it needs to drive the registers in your design.
I think: there is no difference .
sign-off sta must be post-layout sta. When layout is done , the spef parameter file is extracted and the sta is done to decide whether the layout is timing ok for tapeout.
what is the post-layout sta aim to do is also to determine whether...
scan insertion mentor
synopsys's scan insertion tool: dft compiler, bsd compiler is easy to use, but synopsys's membist tool is rather bad, just better than do it manully. Mentor's membist tool: memory Architecture is really excellent and its scan chain generator :fast scan is also excellent ...
before CTS, the clock is ideal for all flip-flops so that the result is not precise. After CTS you should add set_propagated_clock in the sdc file to specify the real clock network latency for all clocks.
how to calculate fifo depth
if the two clock has no relationship, minimum depth is 4 words, you may also see
some design is 3 words, but it is special design, not for general case
at first you should have memory's timing model, and in common it is in the .lib file of your memory. Then you can check the timing of the register linked to the output of the ram to find the read timing .
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