Constraining Multiple clock design

[no_mad]

Hi all,

I'm using Mentor Graphic tools to synthesize my design (Leonardo Spectrum: ASIC and Precision RTL: FPGA).

The problem is I'm not very sure on constraining a multiple clock design. Someone please share with me some TCL scripts (LeoSpec & Precision) on constraining multi-clock design. It will be a good reference for me and to other people.

At least, a guideline on this issue.
Any suggestions and/or advice are most welcome and highly appreciated.

Thanks in advance,
no_mad

 

[r63511]

a point to start with:
create the clock for each domain, set multi-cycle or false path for cross-domain signals, but you must be very cautious that those false paths won't hide potential violations.

 

[zyphor]

pls find this issue in Prime time guide