Path timing report in DC

[cnspy]

In my module, it has a memory. I hope to know the reading process path timing in DC. How to make this report?


Thanks in advance.

 

[zyphor]

at first you should have memory's timing model, and in common it is in the .lib file of your memory. Then you can check the timing of the register linked to the output of the ram to find the read timing .

 

[cnspy]

I have the memory timing module from the foundry.

You mean I should report the input ports to memory path timing and memory to output ports timing then use the memory to caculate the whole critical path?

 

[seanwu]

Memory commonly split the path into:
1) address /control signal ----> read clock
2) read_clock -----> data out

 

[shockie]

I am not sure about this. In geneal, I add some time constraint at the interface of memory accroding to the demand of memory model because the memory timing is guaranteed by foundry.