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thanks for your answer...
the system should be realized in a way that it can be integrated on chip.
so although i like the idea with the oversampling i´m not sure how it could be realized.
a crystal cannot be used. maybe i can transmit a synchronyzing sequence with fast transitions to...
Hello,
I´m going to design a system where a digital signal is transmitted over a wired connection.
the frequency of the signal should be as small as possible to save power.
on the receiver side there will be a digital system that has to be clocked with 4MHz because it has to generate a...
Hey,
the matching problem was discussed here in edaboard but meanwile I found Millikan´s thesis were the missmatch problem was discussed with more detail.
I´m quite sure that stabillity does not have to be affected with a proper design.
Thanks for the hint on Monk´s approach.
I´m still...
Do you have any topology in mind?
I checked several components but there wasn´t any schematic shown inside the datasheet.
I want to design the LDO in a 0.35nm cmos technology.
Hey,
I need to design a capless LDO with a dropout voltage of 0.8V and load currents from 0 to 60mA.
Up to now my first joice would be the Milliken LDO with a current differentiator for compensation.
No I read that this design is very critical due to missmatch.
Could anyone confirm that?
Is...
Hey,
for designing an amplifier I need usually 3 to 4 testbenches. So by time I´m ending up with a lot of testbenches for all my designs.
Now I found this...
**broken link removed**
This would help me to have all testing stuff together.
But I´m not sure how I should modifiy the schematic for a...
Hey there,
I have to drive a big inverter with w/l>1000.
To be able to switch this inverter I´ll put several buffer stages in front.
Is there any rule of thumb how large the previous stage has to be with respect to the next one?
At the moment I don´t care about any delay around 500p or short...
Hello,
I want to switch a 80mA current with an inverter. The transfer characteristic should have smooth slopes so that the input of the inverter is lowpass filtered.
Unfortunally the peaking current gets quite high so that it influences my supply because the time where both switches are open...
so you mean i should simulate one gate and determine its transition time?
this would give me allso the drive strengths of the other gates.
and if one gate with the outputs is not capable of driving a gate it a gate of 2x instead of 1x would double my driving capability?
i´m just not sure how...
hey sathyanarayana,
what you said seams clear to me.
but how do i know how many other gates i can drive with one gate?
or how much drive strength i need to drive a certain number of gates of the output of a gate.
for example i have a nor gate 2x and i want to drive 8 other nor gates with that...
Hello,
i want to do some full-custom digital design.
therfore i have to know the drive strength of the digital cells of my process. (i´m using ams c35).
in the design documents the only information about drive strength is given in 0,5x, x, 2x,...
how can this be translated into a real number...
hey all,
i have a current mirror where the currentmirror is a long l device.
can i spilt this device into several devices with the same width and a shorter l?
what about the current matching when doing it this way?
regards zitty
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