how to find out drive strength of logic gates

[zitty]

Hello,

i want to do some full-custom digital design.
therfore i have to know the drive strength of the digital cells of my process. (i´m using ams c35).
in the design documents the only information about drive strength is given in 0,5x, x, 2x,...
how can this be translated into a real number? or how do i know how many other gates can be driven by such a gate.
does anyone know where to find infromation about this?

regards zitty

 

[sathyanarayana raoh]

hello,
1.current flow or drive strength of the device is proportional to W/L
2.for given channle length L, the larger the width lager the drive capacity
3 to double the drive strength of the device double the channel width or add two 1x device in parallel
4 adding 1x in parallel is prefered y bcoz if we increase the channel width it may affect the std cell heigth and may have some problewms while placing the cells
5. now how to calculate the drive strength.... assume ur channel length is 0.45 and width is 1.5 now drive strength for 1x is 3.33 now 2x =6.666
3x=13.33

 

[zitty]

hello,
1.current flow or drive strength of the device is proportional to W/L
2.for given channle length L, the larger the width lager the drive capacity
3 to double the drive strength of the device double the channel width or add two 1x device in parallel
4 adding 1x in parallel is prefered y bcoz if we increase the channel width it may affect the std cell heigth and may have some problewms while placing the cells
5. now how to calculate the drive strength.... assume ur channel length is 0.45 and width is 1.5 now drive strength for 1x is 3.33 now 2x =6.666
3x=13.33

hey sathyanarayana,

what you said seams clear to me.
but how do i know how many other gates i can drive with one gate?
or how much drive strength i need to drive a certain number of gates of the output of a gate.
for example i have a nor gate 2x and i want to drive 8 other nor gates with that gate. will that be possible without reasonalbe degradation of the singal form?

 

[sathyanarayana raoh]

hello,
1. why do we increase drive strength?
a. improve the slew rate(ii.e reduce slope of the signal)
for ur question i think it is depend upon ur load capacitance of those 8 nor gates..
this is the reason for which we are going for max transition vioaltion and max cap violation...these rules help us to reduce transient power consumption and ensure that the gate loads are stay with in the range of delay models...

 

[zitty]

so you mean i should simulate one gate and determine its transition time?
this would give me allso the drive strengths of the other gates.

and if one gate with the outputs is not capable of driving a gate it a gate of 2x instead of 1x would double my driving capability?
i´m just not sure how the usual design flow works.