Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

reduce peaking current of inverter

Status
Not open for further replies.

zitty

Member level 2
Joined
Aug 2, 2010
Messages
42
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,628
Hello,

I want to switch a 80mA current with an inverter. The transfer characteristic should have smooth slopes so that the input of the inverter is lowpass filtered.
Unfortunally the peaking current gets quite high so that it influences my supply because the time where both switches are open ist quite long due to the filtering.

At the moment I connected both gates togeher and switch it with one source.
I was wondering if it would be possible to put move this node and put some delay (different for pmos and nmos) in between.
Maybe there are other possiblilites I just dont know what I should look for.
Does anyone have me some keywords?

regards Zitty
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top