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cadence post layout simulation error
Can't we simply simulate from the terminal using the command "spectre net_pex.scs" after adding the important lines for including models & viewing outputs?
soi technology
Hi All,
What are the main differences between the normal CMOS technology & the CMOS SOI technology (Silicon on insulator)?
Does it only affect the mos devices? i.e no change in the resistors, capacitors ...
Also for mos devices, what are the main differences between SOI mos &...
skill code for a schematic
sikadiya,
I am not having any errors, but the function is not executed as i expect. I am expecting that the component would be add at the specified location but this doesn't happen. What happens is that the "create symbol" dialog box is opened & the correct component...
a skill code to add instance
Hi,
I want a skill code to add an instance in a schematic sheet.
I tried the following code but it hasn't worked
procedure(
abc(component)
schHiCreateInst("tsmcN90" component "symbol" "I0" 1 1)
mouseAddPt()
0:0
)
then i call this function using:
abc("nch")
I am...
Burst-Mode CDR
Hi,
I need some documents that explain the burst-mode CDR. Of course I have searched the net but I am wondering if you want to recommend a certain one for me. I need a document that explains the concept of operation.
Thanks
Yassin
technology features
Hi,
I want to know why there are more than one design kit for each technology node? For example, for 0.13u there High Voltage PDK, MMRF PDK, LOGIC PDK. Can't we have only one design kit that includes all the available features in the process? I think Analog layout designers...
Is it useful to make initial simulation using level 1 models which uses mos simple equations just as a start with the hand analysis, then we can move to the simulation with its results as ana initial vaue?
Or this will be just time wasting??
circuit design flow
Hi friends,
I am starting to design a folded-cascode fully differential amplifier OTA with CMFB. I am confused and don't know how to start because of the large number of mosfets. I know that the ideal flow is to start with hand analysis then move to the simulation stage...
Re: PLL simulation
Thanks for the simulation results. It seems that the problem is in how i am running the simulation.
I am trying to understand the PLL system more. I want PLL specs that i may try to meet, hence i will gain more knowledge about PLL. You know, reading is not enough. Please...
Re: PLL simulation
You have run the simulation using spice simulator but i am trying to study the system behaviour using matlab (simulink). I am just trying to see how the output phase follows the input excess phase. So I am using a single block with the PLL transfer function to act as the PLL...
Re: PLL simulation
I am expecting to see an output chnaging from 0 to 1 in a smooth way because as i think the PLL acts as a LPF.
Noting that input & output signals represent the excess phase for input & output signals respectively, not the totlal phase.
Hi,
I am trying to simulate the behaviour of a type 1 PLL using simulink, the loop parameters are:
Wlpf=2pi*(1 MHz);
Kvco=100M
Kpd=1
So the loop T.F. is T(s)=(Kvco*Kpd*Wlpf)/(S^2+Wlpf*S+Kvco*Kpd*Wlpf);
I am using three blocks:
1. input block which is a step source to simulate the input phase...
Via shape depends mainly on the foundary rules because via dimensions are fixed for one each process. For example you may find the contact dimensions are 0.12ux0.12u. Another rule in the minimum allowed layer overlaps which determines the shape of the metal that are connected using this via. For...
Hi All,
I haven't read Gary' book. But I think razavi's one is very good because it helps designers to expect the circuit behaviour without so much analysis.
But I have a question, If I read razavi's book, am i in need to read Gray's book? will it add new info to me or it's just a different...
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