Help me find error in PLL simulation using Simulink

[yassin2705]

Hi,

I am trying to simulate the behaviour of a type 1 PLL using simulink, the loop parameters are:
Wlpf=2pi*(1 MHz);
Kvco=100M
Kpd=1
So the loop T.F. is T(s)=(Kvco*Kpd*Wlpf)/(S^2+Wlpf*S+Kvco*Kpd*Wlpf);
I am using three blocks:
1. input block which is a step source to simulate the input phase.
2. "Transfer function" block to act as the PLL loop.
3. Scope block to display the output.
After running the simulation for 5 sec, the output is not meaningful, I don't know if this is a problem of simulation accuracy or not.
So any hints??!

Thanks!
yassin

 

[elbadry]

kvco simulation

What output do you get and what output did u expect to get?

 

[yassin2705]

Re: PLL simulation

I am expecting to see an output chnaging from 0 to 1 in a smooth way because as i think the PLL acts as a LPF.

Noting that input & output signals represent the excess phase for input & output signals respectively, not the totlal phase.

 

[LvW]

Re: PLL simulation

Hi,

I am trying to simulate the behaviour of a type 1 PLL using simulink, the loop parameters are:
Wlpf=2pi*(1 MHz);
Kvco=100M
Kpd=1
So the loop T.F. is T(s)=(Kvco*Kpd*Wlpf)/(S^2+Wlpf*S+Kvco*Kpd*Wlpf);
After running the simulation for 5 sec, the output is not meaningful, I don't know if this is a problem of simulation accuracy or not.

Hi yassin, what do you mean with "not meaningful" ??
As the transfer function was given by you it was not a problem to run an ac analysis of it with a SPICE simulator. Result: 0 db gain with a peak of app. 5 dB at 5 MHz.
This peak corresponds to a pole Q=4 which is rather high for a PLL.
Do you intent to design a loop bandwidth in the order of 4..5 MHZ ?

Added after 5 minutes:

Results from a TRAN analysis (step response): Overshoot of app. 60 %; ringing with app 10 periods until the output settles after 2 usec.

 

[yassin2705]

Re: PLL simulation

You have run the simulation using spice simulator but i am trying to study the system behaviour using matlab (simulink). I am just trying to see how the output phase follows the input excess phase. So I am using a single block with the PLL transfer function to act as the PLL. & I am using a step function as the input excess phase. Then I am trying to see the output excess phase.

So is there any problem with that system? should it work correctly & how to let it work??

Added after 2 hours 44 minutes:

I found this topic which contains some useful information about how to simulate PLLs using simulink.

 

[LvW]

Re: PLL simulation

You have run the simulation using spice simulator but i am trying to study the system behaviour using matlab (simulink). I am just trying to see how the output phase follows the input excess phase. So I am using a single block with the PLL transfer function to act as the PLL. & I am using a step function as the input excess phase. Then I am trying to see the output excess phase.
l

That´s exactly the same as I did. I did use a single block with the transfer function as given by you. In matlab/simulink you should get exactly the same results as I have described in my last reply. Did you ?

 

[yassin2705]

Re: PLL simulation

Hi LvW,

Please find attached my simulink file. Could tell me where is the problem?

Thanks!
yassin

 

[LvW]

Re: PLL simulation

Hi LvW,
Please find attached my simulink file. Could tell me where is the problem?
Thanks!
yassin

Sorry, I don´t work with simulink. I prefer other simulation packages.

For your information I give you my simulation results (pdf attachement)

 

[yassin2705]

Re: PLL simulation

Thanks for the simulation results. It seems that the problem is in how i am running the simulation.

I am trying to understand the PLL system more. I want PLL specs that i may try to meet, hence i will gain more knowledge about PLL. You know, reading is not enough. Please send it to me if you have.

Many Thanks!

 

[LvW]

Re: PLL simulation

I was trying to send you a pdf document showing "my fluctuations" as a result of a PLL simulation - but the posting was not working.
I shall try it again later.