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Recent content by wufengbo

  1. W

    Verilog problem with using defparam

    verilog paramter defparam is synthesisable in synplify, you can try it. but the method of aji_vlsi's is the prefered one. because the defparam construct maybe remove from the future version of systemverilog.
  2. W

    Where to implement an AES encryption/decryption algorithm: in FPGA or in CPLD?

    Re: FPGA or CPLD? I think FPGA is prefered, because FPGA has enough resource to implement the AES algorism.
  3. W

    Looking for materials to learn System Verilog

    request systemverilog You can get some information from h**p://www.accellera.org
  4. W

    what is source synchronous devices..??

    We known, synchronous data transfer is from a SOURCE to a DESTINATION. Traditionally, the clock signal is supplied by a OSC and it distribute the clock signal to both the source and the destination. But with source synchronous system, the clock signal is supplied by the SOURCE. Sorry, I post...
  5. W

    what is source synchronous devices..??

    We known, synchronous data transfer is from a SOURCE to a DESTINATION. Traditionally, the clock signal is supplied by a OSC and it distribute the clock signal to both the source and the destination. But with source synchronous system, the clock signal is supplied by the SOURCE.
  6. W

    how to manage a IC design project

    I think you are right. IC design project is generally like software project. Of course, there are some difference between them. But, for a project perspective, they are the same, I think.
  7. W

    Looking for information about various FPGAs

    which FPGA is better? I think Xilinx'FPGAs are suitable for most real design and they provide better performance than @tera's.
  8. W

    LDV 5: can't find ncvlog.exe error!!

    Maybe you should set Enviroment Variable CDSROOT to the install directory of LDV. and set CHDL_LIB_INST_DIR to %CDSROOT%. Try it,good luck.
  9. W

    LDV 5: can't find ncvlog.exe error!!

    Have you set CDS_ROOT?
  10. W

    Use FPGA to do verification, which product is best ?

    I agree with ramesh and ashishjindal76.VirtexII or VirtexII Pro are both very good device for verification.
  11. W

    Can I use the Done signal in FPGA to reset my design

    If you have no other globle reset in your design,I think the only way is to set INIT attribute.But if you have another globle reset in your design,the initial value is what you specified in reset condition.For example,in the following code,the initial value of 'your_signal' is HIGH.In...
  12. W

    Can I use the Done signal in FPGA to reset my design

    Yes,I agree with you.When DONE goes high,all the user logic in FPGA has been gone into its intial value.
  13. W

    on: design FIFO for packet based data flow

    You must consider following point: (1) synchronous ro asynchronous (2) the threshold for writing and reading. (3) the error packet filtering. (4) the maxium packet length you support. for FIFO design,you can reference www.xilinx.com. I hope this can help you,good luck.
  14. W

    [Req] Testbench by using system verilog with ModelSim

    I think ModelSim don't support systemverilog fully.
  15. W

    can anybody tell mehow to decide skew for a chip ?

    I think you should use timing analysis software to get it .
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