Verilog problem with using defparam

[yasser_shoukry]

I have a problem with using "defparam" with my modules.

I was developing a digital watch module. I developed a counter module to use it inside the digital module.

The counter has a parameter called "max_counts" which is used to define max number of counts after which the counter should overflow:

module counter (clk, reset, counts, clk_out);
.......
.......
parameter max_counts = 4'd9;
.......
endmodule;

Then in the dig_watch module, I instantiated six counters from this module :

module dig_watch(clk, reset, sec0, sec1, min0, min1, hr0, hr1);
.......
.......
defparam C0.max_counts=4'd2;
Counter C0 (...,...,...,....);
......
......
endmodule;

The problem is, when i compile this design on FPGA Advantage , an error message apears at the line of the defparam tells that "using defparam is unsynthesisable"!!!

Can any body help me??

Thanks and Best Regards.
Yasser.

 

[aji_vlsi]

verilog parameters

Yes, defparam is usually non-synthesisable as it uses hierarchical access. Use parameter overriding as:

module dig_module;
counter #(10) c0 ();
counter #(1) c1 ();
counter #(100) c100 ();

HTH
Ajeetha, CVC

I have a problem with using "defparam" with my modules.

I was developing a digital watch module. I developed a counter module to use it inside the digital module.

The counter has a parameter called "max_counts" which is used to define max number of counts after which the counter should overflow:

module counter (clk, reset, counts, clk_out);
.......
.......
parameter max_counts = 4'd9;
.......
endmodule;

Then in the dig_watch module, I instantiated six counters from this module :

module dig_watch(clk, reset, sec0, sec1, min0, min1, hr0, hr1);
.......
.......
defparam C0.max_counts=4'd2;
Counter C0 (...,...,...,....);
......
......
endmodule;

The problem is, when i compile this design on FPGA Advantage , an error message apears at the line of the defparam tells that "using defparam is unsynthesisable"!!!

Can any body help me??

Thanks and Best Regards.
Yasser.

 

[wufengbo]

verilog paramter

defparam is synthesisable in synplify, you can try it.

but the method of aji_vlsi's is the prefered one. because the defparam construct maybe remove from the future version of systemverilog.

 

[anilkumarv]

parameters verilog

defparam is non synthesiable. Moreover using defparam construct is considered to be a bad coding style. However the method suggested by aji_vlsi is quite good.