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Recent content by warlock_ajay

  1. W

    FPGA VGA controller output "problem"

    Hello Guys, I am trying to use the VGA display in a project using FPGA board. At the moment I am working on Basys2 FPGA kit from Digilent Inc, link www.digilentinc.com/Data/Products/BASYS2/Basys2_rm.pdf that uses spartan3 FPGA. Digilent Inc. - Digital Design Engineer's Source I tried making a...
  2. W

    Problem with the integrator circuit

    Hi I am trying simple integrator circuit with cadence using op-amp from its generic analog library (ahdl lib). This simple design works fine with sine input that I get nice cosine output. But feeding it with a pulse source doesn't result in an expected triangular wave. Does anyone see anything...
  3. W

    significance of positive feedback in op-amp based non-invert

    Re: integrator Hi see this link: https://www.allaboutcircuits.com/vol_3/chpt_8/12.html
  4. W

    Differential Amplifier (CMOS) design dc analysis problem

    OK this is what I have done finally, I put feedback through a resistor and now I get what I wanted!
  5. W

    Differential Amplifier (CMOS) design dc analysis problem

    Thank u checkmate. You are right. I brought the current in current source I2 down from 105u A to 95u A. Now none of the transistors are in linear region. I setup circuit for differntial sweep again and none of the transistors are in linear region and I get the ouput (snapshot). With resistive...
  6. W

    Differential Amplifier (CMOS) design dc analysis problem

    Hi @checkmate- I have tried your suggestion and here are the outcomes. Please see if I have setup in a right way. 1. Vtp=-0.72044, Vtn=0.59241 2. Vdd is 3.3V according to the tech manual and model 3. I shorted inputs to 1.65V and ran DC anlysis. (results -snapshot) M7 and M4 are in linear...
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    Differential Amplifier (CMOS) design dc analysis problem

    @Checkmate Sorry about that vague description. Let me make the circuit, simulate and quote again. Vdd 3.3V Vss 0V V24 at inv input V23 at non-inv input I am sweeping V24 from 0V to +3.3V while keeping V23 at constant 1.65V. I am checking currents at nodes M1 & M2. when sweep goes from 0V to...
  8. W

    Differential Amplifier (CMOS) design dc analysis problem

    Hi Tell me if I am wrong. If I sweep from -ve to +ve, the voltage difference between the inputs of the differential amp reverses, so initially the current at M1 is equal to the tail current (M2 current 0) as the sweep passes 1.3V the polarity reverses at the differential input and now M1 must...
  9. W

    Differential Amplifier (CMOS) design dc analysis problem

    Thank you for the reply guys I really appreciate that. I also tried to put additional dc to counterbalance offset. Are we not expecting similar response curves for the currents after 1.3V as well? I mean, similar but opposite aroound 1.3V.
  10. W

    DC operating point of differential amp in Spectre

    hi @ erikl and @ checkmate I have similar problem here. But, my differential amplifier is rather simple. No matter what I do it can not take both the NMOS transistors to saturation. the tehchnology is UMC 180 CMOS 3.3/1.8 and I am trying to build the differential amp around 3.3V Vdd. In this...
  11. W

    Differential Amplifier (CMOS) design dc analysis problem

    Hi I have started making differential amplifier and there is some problem with the dc analysis. The currents at the drains of the two bottom NMOS transistors are not behaving in a manner they supposed to. I get gain and bandwidth half of the specifications I started with. Please help. The...
  12. W

    opamp design problem !!

    Thank you guys. I am trying to start it from the cratch now, from the CMOS differential pair to see that I do things right. There seem to be a problem, pls see the snapshots. From -1 to 1 dc, the current curves are not looking good! And so I get half the gain and half the bandwidth of what I...
  13. W

    synopsys- vcs to design_vision

    Hi, Few questions here. Please help. I am working with some FDK, let's say UMC 180 CMOS (pls correct me if I am wrong) vcs: 1. I start with an rtl code and simulate it. Q. Do I need to include the libraries for simulation from the FDK at this point? How? Q. In synopsys_sim.setup, what...
  14. W

    opamp design problem !!

    I am trying to design an opamp and I am a newbie. I don't get any bandwidth and there is some clipping in the signal. If I try to increase the gain by increasing the size of M1-M4, the frequency response looks like a high pass. I am totally lost, please help.
  15. W

    multiple task call in verilog

    the warning says the input inA is never used I am expecting two serial registers but I get only one. Code: module register(out1,out2, inA,inB,clk,reset); output out1,out2; input inA,inB; input reset, clk; reg out1,out2; reg in1, in2, in3; always @( negedge clk) begin regist (out2,inB)...
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