DC operating point of differential amp in Spectre

[design_oriented]

Hi Guys,

I am trying to check the regions of operation for a differential CMOS opamp in Cadence spectre. I can see the regions as 0,1,2,3 but I am having some problems in applying the inputs for the differential amplifier to get the DC operating points for every transistor in the design.

My configuration is a fully differential folded cascode with differential PMOS and NMOS input transistors shown in the picture below.

To get the DC operating point, do I connect one inverting terminal of the PMOS and NMOS to +1V and another to -1V?

Any help in trying to understand how to bias the differential amplifier to see the DC operating regions is greatly appreciated.

Thanks.

 

[rfsystem]

The shown jpg does not contain a cadence annotated schematic with "region" attributes.

Could you supply the right one.

 

[design_oriented]

Thanks for the feedback.

Attached are two pictures showing DC and AC simulations.

The DC simulation has been done with negative DC voltage sources V0 and V4 applied to the PMOS differential inputs and the NMOS inputs kept floating.
V0 is swept from 0-1V DC and V4 is kept constant at 1V DC.

In this I do not get M0, M12 and M6 in saturation. I tried playing with the W of the PMOS but it did not change the region to saturation.

Is this the right approach to perform DC simulation?

I have done the same for the NMOS inputs (making the inputs positive DC) with the PMOS input floating.

Also attached is the A.C. simulation for an input sine wave of 10mVpp at 20 MHz. I have showed the W/L for the transistors.

Any ideas how I can get the transistors in saturation?

Thanks again for your help.

 

[diemilio]

So, you're running a DC sweep but you're just checking the transistors' "regions" using the annotated values which means that you're not really doing anything by sweeping the voltage. Since you're simulating in an open loop configuration, what you have to to is either run a closed loop sim to fix the input DC potentials, or by using your DC sweep results, find the saturation point of operation and use the input DC offset in your voltage supplies so that the right values get annotated.

diemilio

 

[design_oriented]

Thanks for the reply,diemilio.

I will try removing the sweep and only apply the dc. to both the inputs for the simulation.

So when I check it in closed loop mode, should I connect the output to the negative input and ground the positive input and then run the DC simulation?

 

[erikl]

The n-well taps of the M20 & M21 PFETs are erroneously connected to GND. That's why the high currents ( > 3mA) through M7 & M10 are short-circuited by the forward-biased source-to-bulk diodes of M20 & M21 to GND.

For normal operation and the simulation, both inputs should be DC biased to vdd/2 .

 

[design_oriented]

Thanks for the feedback. With the correct PMOS connection, all transistors except M0 and M3 are in saturation. M0 and M3 are in the linear region.

I have tried changing their W's but I cannot get them in saturation. Do I need them in saturation?

Thanks again for your help.

 

[erikl]

I have tried changing their W's but I cannot get them in saturation. Do I need them in saturation?

Yes, otherwise you loose a lot of the possible gain. I think they are too wide. Try and give them the same widths as their counterparts, i.e. WM0=WM10=WM7=30µ and WM3=WM16=WM4=10µ . And may be even (all of these) a bit less.

 

[design_oriented]

Ok thanks. I changed that and it worked.

I know you had suggested a pdf file which showed a testbench circuit but I would like to know how I can measure AC and DC gain with the configuration I have?

Do I have to connect the output to the negative input and apply the AC input to the positive terminal?

Also do I need a DC offset (= VDD/2) in my AC input?

Thanks again for your help.

 

[erikl]

Ok thanks. I changed that and it worked.

Congratulations!

Do I have to connect the output to the negative input and apply the AC input to the positive terminal?

Connect the output via an iprobe symbol from the analogLib (Analysis Category) to the negative input. This ensures full DC and no AC feedback (for an open loop analysis).

Also do I need a DC offset (= VDD/2) in my AC input?

Definitely, yes! Use a vdc source with DC voltage=VDD/2 & AC magnitude=1 . Then run an AC analysis from - say - 1Hz ... 1GHz .

Good luck!
erikl

 

[design_oriented]

Ok sorry I just noticed that M3 is not in saturation but in linear region.

I have all PMOS with W = 30 and all NMOS with W = 10.

How can I get the M3 NMOS in saturation region?

 

[erikl]

I think all your current source MOSFETs (M3, M16, M4, M0, M10, M7) are too wide. But instead of reducing their widths I'd rather extend their lengths (e.g. from 0.18 to 1 or even 2µm), because of better matching.

On the other hand I think your differential input MOSFETs (M2, M11 & M12, M6) are not wide enough: I'd try and give them at least the same widths as the cascode (output) MOSFETs (i.e. NMOS W=10 and PMOS W=30). At least if you are interested in low noise.

 

[checkmate]

The reason is that there is something really wrong with your tail current bias. Assuming the opamp DC output is vdd/2, that will mean both your tail transistors are ALSO biased at vdd/2, which is a huge overdrive, hence forcing both into linear. if you skew your opamp DC output, you can put one of them into saturation, but the other one will be pushed further into the linear region.

You should really try with the standard rail-to-rail input configuration before trying out other fanciful architectures. This architecture seems to have too many loops, and even if you manage to get the DC right, stability will be an issue.

 

[erikl]

Hi checkmate,

this circuit stems from a well known paper (Song et al. , s. below, Fig. 3 on p. 2), allegedly has been fabricated in a 0.6µm std. n-well process @ ANAM, and should work well for power supply voltages between 1.8 and 3.3V , s. the PDF below, p. 3 . One just needs the right sizing!

 

[checkmate]

Let's just consider the N-side tail current, for the simple case where both input and output common mode are equal to VDD/2. It is biased at VDD/2, giving it an overdrive of VDD/2-Vth(M3).
The drain of the tail node at DC is VDD/2-Vth(M1)-Vov(M1).
This drain voltage must be greater than the overdrive of M3 for M3 to stay in saturation, which gives Vov(M1) < Vth(M3) - Vth(M1).
Now, unless M1 and M3 use transistors with different thresholds, it's gonna take humongous transistors to "maybe" get M3 into saturation. Skew the inputs and/or the outputs and you will push M3a further into the linear region.
I have named all transistors in relation to the paper. Nevertheless, things just dont add up to me.

 

[erikl]

You're right, checkmate, thank you, I didn't yet consider that. M3 (and all the other tail current FETs) could only stay in saturation, if the transistors in between (the proper active cascode ones) would determine the current (i.e if the current through the tail current FETs would be much lower than their short circuit current) - but this is not desirable, of course. Also, the output swings (noted on p. 3 of the paper given above) demonstrate that the tail current transistors can't stay in saturation - at least not when the output is close to the pwr supply rails - in contrary to the statement on p. 2 of the paper.

At 1.8V power supply, the reported gain of 80dB (p. 3) is rather high. Its strong decrease with higher supply voltages (gain ≈ 60db @ VDD=3.3V) shows its dependence on less and less "saturation" (or falling ro) of the tail current FETs with the VDD/Vth ratio.

But it still seems quite a good OTA architecture for low supply voltage applications, considering the self-biasing feature. I wish I could analyze the circuit, but currently I'm lacking access to the C@dence licenses :-( . Hopefully, the OP will find the right sizing for his process!

 

[design_oriented]

Hi Guys,

I could get all the transistors in saturation except M6 and M12. No matter what I do (change width and length) those two continue to stay in the linear region.

I have decided to move on with the AC simulations.

I am trying to get the gain. However I am confused here.

Should I measure the gain separately first with the NMOS (with the positive 0.9V dc voltage to both NMOS inputs) and then repeat it with the PMOS with -0.9V?

I am connecting the output through a current source to the negative input and then connecting a Vdc input with AC magnitude of 10 mV. How can I sweep the frequency of this to get the frequency response? As the resistance of the current source will be very high this is open loop gain right?

Thanks again for your patience and help.

 

[design_oriented]

Anybody have any comments on this?

 

[warlock_ajay]

hi

@ erikl and @ checkmate

I have similar problem here. But, my differential amplifier is rather simple.

No matter what I do it can not take both the NMOS transistors to saturation.
the tehchnology is UMC 180 CMOS 3.3/1.8 and I am trying to build the differential amp around 3.3V Vdd. In this case Vss=gnd.

If I were to consider the rail to rail design, is it possible? I don't understand how you can have -3.3 to 3.3 supply when you have 3.3V available. Is that you just reverse the polarities of the supply to the Vss? Please elaborate on this.

If it is possible to use rail to rail supply, I might go for this option. However, I would like to make this circuit work.

Please help.
Thanks.

 

[erikl]

I don't understand how you can have -3.3 to 3.3 supply when you have 3.3V available.

Normally, you can't! But see below.

Is that you just reverse the polarities of the supply to the Vss? Please elaborate on this.

Normally, this isn't done within an IC. It is, however, possible to create a negative "power supply" from a positive one within an IC (mostly used as an auxiliary voltage, e.g. in DRAMs); in such case, the substrate must be connected to the most negative potential level - as always.

If it is possible to use rail to rail supply, ...

There's no such thing as a rail to rail supply: A supply is a supply is a supply - nothing else. You can have rail to rail input voltage range or r2r output voltage range - or both.