multiple task call in verilog

[warlock_ajay]

the warning says the input inA is never used
I am expecting two serial registers but I get only one.

Code:
module register(out1,out2, inA,inB,clk,reset);
output out1,out2;
input inA,inB;
input reset, clk;
reg out1,out2;
reg in1, in2, in3;
always @( negedge clk)
begin
regist (out2,inB);
regist (out1,inA);

end
/*always @( negedge clk)
begin

regist (out2,inB);
end*/
task regist;
output out;
input in;
begin
in1 <= in;
in2 <= in1;
in3 <= in2;
out <= in3;
end
endtask
endmodule

 

[vipinlal]

always @( negedge clk) 
begin 
regist (out2,inB); 
regist (out1,inA); 

end

I dont know VHDL.But I think you cannot port map inside always statement.
Remove the always statement.Instead give a always statement in the reg module itself.

--vipin
https://vhdlguru.blogspot.com/