Differential Amplifier (CMOS) design dc analysis problem

[warlock_ajay]

Hi

I have started making differential amplifier and there is some problem with the
dc analysis. The currents at the drains of the two bottom NMOS transistors
are not behaving in a manner they supposed to.

I get gain and bandwidth half of the specifications I started with.

Please help. The Snapshots are posted for assistance.

 

[prcken]

i think the currents at the source of the two bottom NMOS transistors
are behaving good as you ramp the voltage.

 

[erikl]

The currents at the drains of the two bottom NMOS transistors
are not behaving in a manner they supposed to.

I guess: due to offset.

 

[warlock_ajay]

Thank you for the reply guys I really appreciate that.

I also tried to put additional dc to counterbalance offset.
Are we not expecting similar response curves for the currents after 1.3V as well?
I mean, similar but opposite aroound 1.3V.

 

[prcken]

actually i am confused by the way you add stimuli for DC analysis. you just need to put a DC source between the positive input node and negative input node, and sweep the voltage.
from the current curves, i think it's reasonable as one side of the NMOS is cut-off, the tail current is all flowing into the other side.
what kind of the curves you are expecting to get?

 

[warlock_ajay]

Hi

Tell me if I am wrong. If I sweep from -ve to +ve, the voltage difference between the inputs of the differential amp reverses, so initially the current at M1
is equal to the tail current (M2 current 0) as the sweep passes 1.3V the polarity reverses at the differential input and now M1 must be off and M2 must start to conduct with M2 conducting all the tail current and M1 current 0.

In fact, I am getting half the gain and bandwidth (because of this?)

So I should get the current curve similar to the one in this pic I pulled off the internet.

Please correct me if I am wrong and tell me how to get curves as shown in this pic.

BTW, dc sources V20 and V21 are for the differential input. V19 is for the Vcmin=1/2(Vdd-Vss) (if I dont put this I get weired curves). Finally, V22 is for the offset.

Cheers.

 

[checkmate]

Firstly, I dont see any need to deliberately include an offset.
Secondly, a clearer explanation of your problem would be good. Your first post showed that some vdc was swept. Which one? Your last post mentioned "something" was swept from +ve to -ve? What is it?

Just list down your common-mode input, which voltage source was swept, and the sweep range.

Lastly, voltage and currents are 2 very different quantities. You shouldnt expect their curves to be the same. Mind sharing what kind of current profiles for the input stage are you expecting?

 

[warlock_ajay]

@Checkmate

Sorry about that vague description. Let me make the circuit, simulate and quote again.

Vdd 3.3V
Vss 0V
V24 at inv input
V23 at non-inv input

I am sweeping V24 from 0V to +3.3V while keeping V23 at constant 1.65V. I am checking currents at nodes M1 & M2.

when sweep goes from 0V to 1.65V, current at M2 starts from 0uA and gradually rises to ~50uA and at M1 current starting from ~90uA gradually falls to ~50uA. When sweep further goes up to 3.3V the currents at M1 & M2 are both ~50uA.

Should it not be that after 1.65V the currents, M1 falls further down to 0uA and current at M2 rise further up to 90uA giving sort of symmetrical curves around 1.65V (x-axis)? I expect the current curves to be like one in the sample snapshot.

Thanks

 

[checkmate]

Several points you may try out.
You seem to have a headroom issue. Though biased with a 105u current, the total current from the input pair never reaches that value. Are you sure your process is targeted for 3.3V operation? The best way to check is to short the inputs to 1.65V, run a dc analysis and check the operating regions of all transistors, in particular M7, M1, M2 and M4.
Since you loaded out2 with a cap, why not do the same to out1?
And instead of fixing V23 at 1.65V, configure V23 to output 1.65-x and V24 to output 1.65+x. This will ensure that the common mode stays at 1.65V.
Any idea what is the threshold voltage for your process?

 

[warlock_ajay]

Hi

@checkmate-

I have tried your suggestion and here are the outcomes. Please see if I have setup in a right way.

1. Vtp=-0.72044, Vtn=0.59241
2. Vdd is 3.3V according to the tech manual and model

3. I shorted inputs to 1.65V and ran DC anlysis. (results -snapshot)

M7 and M4 are in linear region.

What next?

 

[checkmate]

The gate of M2 is shorted to gnd and not 1.65V.
If you observe M8, it has a pretty large overdrive of around 0.6V. This would imply that M7 needs at least a vds of 0.6V to remain in saturation.
You calculate the common-mode input range.
vicm(min)=vdsat(M7)+vgs(M1) which is approximately 1.3V.
vicm(max)=vdd-vdsat(M4)-vdsat(M2)+vgs(M2).
On top of that, because the gain is very large, M2/M4 will only remain in saturation for very small differential inputs. And remove the cap on out1. Apologies on that, too tired to think straight.

 

[warlock_ajay]

Thank u checkmate.

You are right. I brought the current in current source I2 down from 105u A to 95u A. Now none of the transistors are in linear region.

I setup circuit for differntial sweep again and none of the transistors are in linear region and I get the ouput (snapshot).

With resistive load and low value of overdrive for M7, I get what I am looking for (snapshot). I expect similar results using PMOS. It is alright to drop gain a bit.

 

[warlock_ajay]

OK this is what I have done finally, I put feedback through a resistor and now I get what I wanted!