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Recent content by VishwanathAmbli

  1. V

    555 Timer Design procedure???

    Sherazi, I know the working and operation in astable/monostable mode. I can design for external components. What i asked for was the internal transistor level design.
  2. V

    555 Timer Design procedure???

    hello all, I want to design 555 timer, ie tlc555 internal circuit. I have internal circuit from data sheet and now to find w/l ratios for each mosfet. I need help on how to go about it, like what parameter to consider.I am attaching data sheet with this post so that you can have a look at...
  3. V

    what is the working of pmos and nmos in an inverter when input is giving to 2.5V?

    (d) none of these.... de both will be in saturation region, try substituting vin, vdd, gnd, values in the eqtns like Vgs-Vth>Vds which helps you to decide the region of the mosfet..
  4. V

    vhdl code for frquency divider by 2,3,4,12

    this is the code for freq/3 , you can implement /2,/4 by just using flipflops or counters.... divide by even number is easy... implement a counter a jst output from one pin of the counter and you have ur freq/2 /4 etc... - - - Updated - - - this is the code for freq/3 , you can implement...
  5. V

    SPI bus Protocol in VHDL

    input will be sampled on the rising edge of sclk means??? it will be read that time or wat... i mean wat variables do we need to implement this in VHDL??? should i have master buffer and slave buffer to store data, n to which variable should i shift to during falling edge... if you can explain...
  6. V

    SPI bus Protocol in VHDL

    hello FvM, in SPI for every rising edge of sclk one bit of data is sent or 8bits????? and if u can help me frame exact entity structure and give the procedure for further proceedings i ll continue with the architecture: thank you... if not entity atleast FSM....
  7. V

    SPI bus Protocol in VHDL

    I am implementing SPI bus protocol in vhdl, the data should be transmitted during +ve rising edge of clock i have written this code but i am unable to get the desired result, am i implementing the right way or no???? any help is appreciated: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use...
  8. V

    VHDL Comparator 4-bit

    use begin after the the process and end process; where the process block ends... try this:
  9. V

    VHDL Comparator 4-bit

    you have written Behv at the inception of architecture but at the end you have used Behavioral so just check with this:
  10. V

    logical and operation

    some and where... n i didn't get ur statement "Please read the statement again. The statement is saying 01 is logic zero. Is not it?" which statement u want me t read again??? specify it
  11. V

    logical and operation

    01 is nothin but decimal 1 wch is not zero, so the statement is true... if a number has sm value other dan zero.... n if u write a statement like if(num) wr num is any value except zero... this results in true :
  12. V

    - Implement this functions with decoder 4:16

    hello, in 2:4 decoder u get 4 outputs but according t ur func, u ve a single output... was dis question asked t u or it was ur own doubt???? i think u need t rethink on the question: i couldn't implement dis func with 2:4 decoder... but i could do it wid 2:1 mux, ll dat help u???
  13. V

    ubuntu 10.04 help regarding bluetooth!!!

    hello, I m using dell inspiron N5010, i ve installed ubuntu 10.04 OS in ths system.i ve also installed bluetooth software 4m software centre but my bluetooth isn't working. whenever i click on bluetooth manager it says "Bluez daemon is not running, blueman-manager cannot continue." it...
  14. V

    Need a verilog code for the follwoing..please help

    this is the main vhdl code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all...
  15. V

    - Implement this functions with decoder 4:16

    define ur problem statement again... bcoz title says 4:16 and u mention 2:4... so define exactly wat u want t achieve and wch gate u want t use t accomplish the task... n how many decoders need t b used etc etc... give complete information...
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